Kanji Otsuka

Integrated circuit package having heat sink bonded with resinous adhesive

An integrated circuit package produced by bonding a rear surface of an insulating substrate enclosed in the package to a heat sink such as a cooling fin by a resinous adhesive, which may include one or more fillers, having a Youngs modulus of 500 kg/cm2 or less when formed into a film, has high reliability at the bonding portion and withstands without damages even if subjected to thermal shocks.

A New Silicone Gel Sealing Mechanism for High Reliability Encapsulation

Plastic molded packages for large-scale integrated (LSI) devices are widely utilized for low-cost computer equipment. The environmental reliability of conventional plastic molded packages, however, is inferior to the reliability of hermetically sealed ceramic packages. A sealing mechanism for the chip, using a silicone jelly as an encapsulation, is discussed.

High reliability and low cost in plastic PGA package with high performance

A 595-pin P-PGA (plastic-pin grid array package) was developed for a high-pin-count LSI. The reliability of the 595-pin P-PGA was investigated by means of temperature cycling, and moisture resistance and electromigration tests. The lifetime until 0.1% failure under temperature cycling is determined to be from 2500 to 2700 cycles. There was no failure in moisture resistance and electromigration tests. The electrical characteristics of 595-pin P-PGA were improved for a high-speed operation LSI. As a result, in addition to the fundamental design, a 595-pin P-PGA with eight metal layers was developed, which is suitable for a 50-MHz operation LSI under 3.3-V power supply.<<ETX>>

Package design for high-speed low-cost ASIC LSIs

Cofired alumina ceramic, alumina-based Cu/polyimide thin films, and plastic PGAs (pin-grid-arrays) are compared in terms of electrical and thermal characteristics and cost. Plastic PGA with the cavity down and a three-layer structure is shown to be the best way to meet the requirement of over 50-MHz signal transmission, thermal resistance and cost. The best results on the 592-pin plastic PGA package and its simulation results are described.<<ETX>>

The technology for over 300-pin QFPs

By merely changing the lead frame structure, high-performance QFPs (quad flat packages) were developed without any new technology. This technology makes successfully up to 304-pin QFPs. The lead frame structure is two layers for a high-speed signal and even for thermal management. The outer lead pitch is 0.5 mm. The 28-mm and 40-mm square body sizes are achieved in such a high pin count. The approach leads to low cost and high productivity and reliability.<<ETX>>

An advanced step for the conventional CMOS ASIC package

A ceramic pin grid array (PGA) with improved 40- mu m-line thin-film aluminum metallization is described. Fine pitch bonding on 120- mu m centers has been successfully implemented. The 400-pin array package is no larger than the previous 240-pin packages. Worst-case capacitances of 1.94 pF, and inductances of 8.5 nH, have been achieved with further reductions possible. The thermal resistance of the package is 6.5 degrees C/W using an aluminum cap with aluminum fins and solder glass sealing.<<ETX>>

Development of PWBs with resin composite capacitors for RF module substrates

Radio frequency (RF) modules have been miniaturized rapidly due to the increasing demand for compact wireless applications such as cellular phones. RF modules involve many passive devices for decoupling, filtering, and matching impedance. RF designers have been seeking space for these passives. The technology of passive embedment in boards is one of the solutions to meet smaller device space requirement. In this paper, we describe the structure of and the process for printed wiring boards (PWBs) with embedded capacitors. The high frequency properties of the capacitors are introduced including the scattering parameters (S-parameters). In addition, their equivalent circuit models and simulation results are discussed.