Kannan Babu Ramia

Understanding the bottlenecks in virtualizing cellular core network functions

Network function virtualization (NFV) promises significant cost savings, flexibility and ease of deployment. However, potential challenges in implementing virtualized network elements that can support real-world performance requirements are still an open question. For example, traditional telecom networks have a lot of complex interdependencies that can affect performance. In this paper, we study the potential bottlenecks in virtualizing cellular core network functions. Using a combination of analysis and experimentation, we quantify the impact of software-based EPC elements on various metrics including physical processing, memory, IO, and bandwidth resource requirements. We use production grade, software-based cellular network elements running on general purpose Linux servers, driven by a variety of realistic workloads derived from a realworld cellular network, to examine the combined effects of control and data planes on an LTE enhanced packet core (EPC). In particular, we discover that the SGW handles about 33% of the control plane transactions and is a potential source for performance bottlenecks as a result of the interdependencies between control and data plane processing. Our results indicate that simply replacing existing EPC elements with virtualized equivalents can have severe performance bottlenecks and that virtualized EPC elements need to be carefully designed.

High-performance evolved packet core signaling and bearer processing on general-purpose processors

Telecommunications service providers are exploring the use of standard high-volume servers to reduce total cost of ownership while at the same time increasing flexibility, service velocity, and scalability of network functions. This article characterizes performance of general-purpose processors - specifically x86 architecture processors - for signaling and bearer processing representative of a wireless carriers call model for a Long Term Evolution Evolved Packet Core. A radio access network emulator was used to stimulate an Evolved Packet Core software stack running on an x86 server. The goal was to prove that standard high-volume servers can execute EPC functions per representative market call models, and that workloads can scale across bearer and control plane at line rate without acceleration technologies. A call model was developed to quantify the performance on Intel® Xeon® Processor based servers using an LTE traffic simulator and a commercial EPC software stack. The traffic models represent bidirectional real-world network traffic during different times of the day. The results were that the test EPC processed control and user plane traffic with 50,000 subscribers with a total payload of 10 Gb/s downlink + 4.8 Gb/s uplink traffic using five cores for the data plane and eight cores for the rest of the system; and the user plane throughput scaled in a single blade environment to 20 Gb/s per socket or 40 Gb/s for a dual socket blade.

Integration of LwIP Stack over Intel(R) DPDK for High Throughput Packet Delivery to Applications

Performance of generic operating system like Linux based IP stacks on multicore processors is much less than that of the purpose built IP stacks from the commercial stack vendors which typically run on a SoC/ASICs/Network processor. The issue of under-utilization of hardware resources arises from the fact that the generic IP stacks operate with much higher overhead, thereby decreasing the overall system performance compared to the capability of the underlying hardware. With Intel multicore processors, its possible to transition from using discrete architectures per major workload (application, control, packet, and signal processing) to a single architecture that consolidates the workloads into a more scalable and simplified solution. This is possible, in large part, due to the Intel Data Plane Development Kit (Intel DPDK), a set of data plane libraries that can improve packet processing performance by up to ten times compare to processing capabilities by traditional OS. Users can integrate their own custom IP stacks with the Intel DPDK and get the advantage of accelerated performance of the Intel DPDK to their applications. This paper explains integration of a version of Light Weight TCP/IP (LwIP) stack with Intel DPDK to extend high packet processing capabilities of Intel DPDK to application layer level and measuring the performance capabilities of DPDK-LwIP network stack.

An IoT control plane model and its impact analysis on a virtualized MME for connected cars

IoT drives the future of Connected Cars including smart cars and it will transform the way we interact with our vehicles. With the emergence of millions of connected cars in the horizon, the wireless infrastructure needed to support this capability has to scale efficiently. To better understand the impact on the resource utilization of the wireless core infrastructure, we provide a detailed statistical model of the control plane/signaling interactions in connected cars. Specifically, our model is based on a 40K sample data set spanning more than 2100 IoT vehicles collected over 20 hours from a national telecommunications provider. The control plane model quantifies the additional load that the infrastructure (e.g., MME) needs to handle compared to an average busy hour LTE traffic model. We identify the heavy hitters of the control plane events and run real experiments based on our models in a testbed to characterize the resource utilization for supporting total event loadings using a real world high performance virtualized MME. No personally identifiable information (PII) was gathered or used in conducting this study. To the extent any data was analyzed, it was anonymous and/or aggregated data.