Kaouther Gasmi

Performance evaluation of MATLAB/Simulink models for fitting embedded multicore systems

The embedded software systems are first designed and validated by high level models such as MATLAB/Simulink functional models. However, implementing a Simulink functional model on multicore architecture is not trivial. Designers might need first to select an adequate multicore architecture that provides a higher performance for a given Simulink model. Hence, it is important to have a set of performance metrics at hand that assist the designers to select the adequate architecture. This paper presents an approach to evaluate the performance of a given Simulink model running on multicore architecture. For this purpose, a given Simulink model is mapped to synchronous dataflow graph, the graph is then scheduled with objective to minimize it iteration period, resulting in performance metrics such as speedup and efficiency. Based on these metrics, an industrial Simulink models is analyzed and a fitting multicore architecture is proposed.

Core number optimization based scheduler to order/map hardware/software applications

Over these last years, the number of cores witnessed a spectacular increase in digital signal and general use processors. Concurrently, significant researches are done to get benefit from the high degree of parallelism. Indeed, these researches are focused to provide an efficient scheduling from hardware/software systems to multicores architecture. The scheduling process consists on statically choose one core to execute one task and to specify an execution order for the application tasks. In this paper, we describe an efficient scheduler that calculates the optimal number of cores required to schedule an application, gives a heuristic scheduling solution and evaluates its cost. Our proposal results are evaluated and compared with Preesm scheduler results and we prove that ours achieves better scheduling in terms of latency and number of cores.

Workflow for NoC/DSP multicores-based platform: From Matlab/Simulink models to hardware mapping and scheduling

Programming multi-cores based Digital Signal Processors (DSP) becomes increasingly complex. This complexity is related to the rapid evaluation of Telecommunication and multimedia systems accompanied by a rapid increase of user requirements in terms of latency, power computation, consumption, etc. Workflow showed to be a successful approach for programming the applications based on NoC-DSP platforms. The main goal of this work is the design of a hardware/software system in an automated manner. In this paper, we present our proposed workflow taking as entry point a Simulink file (.mdl or .slx) derived from embedded Matlab functions. This workflow allows an automatic transformation from a Simulink model to synchronous dataflow (SDF) model, followed by a mapping and scheduling steps in order to obtain the C code to be executed by each core within the designed platform. Our approach is based on the synchronous and hierarchical behavior of both Simulink and SDF, aiming to simplify the generation of a compatible c code for a Noc-DSP platform.

An efficient scheduling and mapping using SMT solver and translating workflow of Matlab Simulink model to synchronous dataflow graph for multi-core DSP architectures

The design of emerging complex embedded real time systems adopts increasingly the concept of multi-core architectures. These systems present a complicated used applications, like the rapid evaluation of multimedia systems, signal processing, telecommunications, and automotive. However, key issues of system designing are tasks mapping and scheduling, memory architecture, and on-chip interconnects. While respecting the requirements of users quality in terms of execution time, latency, buffer size, energy, number of cores, etc. This paper shows a new technique of scheduling algorithm using the Satisfiability Modulo Theory (SMT) solving technologies which aim to minimize the latency with an optimal number of cores. SMT solvers are heavily influenced by the industrial needs and applications. The software part is modeled by the dataflow graphs in multi-core applications. In fact, Workflow is advised to be a successful method to program multi-core platforms. We propose a novel Workflow for an automatic transformation from a Simulink model to a synchronous dataflow (SDF) model. This automation presents efficient results in the latency metric which proves that 4-cores architecture is more efficient than 16-cores architecture on high communication delay.

Workflow for multi-core architecture: From MATLAB/Simulink models to hardware mapping/scheduling

Programming multicore based Digital Signal Processors (DSP) becomes increasingly complex. This complexity is related to the rapid evaluation of Telecommunication and multimedia systems accompanied by a rapid increase of user requirements in terms of latency, power computation, consumption, etc. Workflow showed to be a successful approach for programming the applications based on multi-cores DSP platforms. The main goal of this work is the design of a hardware/software system in an automated manner. In this paper, we present our proposed workflow taking as entry point a MATLAB/Simulink application. This workflow allows an automatic transformation from a Simulink model to synchronous dataflow (SDF) model, followed by a mapping and scheduling steps in order to obtain the C code to be executed by each core within the designed platform. Our approach is based on the synchronous and hierarchical behaviour of both Simulink and SDF, aiming to simplify the generation of a compatible C code. We present also a performance analysis to find an optimal number of cores to be used for a configured MIMO OFDM LTE that we give as example.