Karlheinz Hafner

Design and test of an integrated cryptochip

A self-testing cryptographic coprocessing chip that provides high security for any data protected through its use is described. The design philosophy and chip architecture are examined. Detailed design and test methods and solutions are given, and it is explained why the chips design interacts well in networks and with secure hard disks.<<ETX>>

SMART: tools and methods for synthesis of VLSI chips with processor architecture

A design environment supporting processor synthesis in data-path style is presented. The programming model of a processor described in Common Lisp is transformed into a hardware structure by tools integrated into this environment. The generation of alternative designs is supported by the interactive graphical manipulation of behaviour and hardware structure representations and their correspondences. The synthesis procedure is explained using an example.<<ETX>>

Eine flexible Entwurfsumgebung für RISC-änliche Prozessorarchitekturen

Beim Entwurf von Rechensystemen setzt sich der Trend zum Einsatz anwendungsspezifischer integrierter Schaltungen (ASICs) durch. Handelt es sich bei diesen um Prozessoren, findet mehr und mehr der RISC-Entwurfsstil Anwendung, der einen fur das jeweilige Anwendungsgebiet masgeschneiderten, moglichst einfachen Befehlssatz nahelegt.