Karthik V. Aadithya

Efficient computation of the shapley value for game-theoretic network centrality

The Shapley value--probably the most important normative payoff division scheme in coalitional games--has recently been advocated as a useful measure of centrality in networks. However, although this approach has a variety of real-world applications (including social and organisational networks, biological networks and communication networks), its computational properties have not been widely studied. To date, the only practicable approach to compute Shapley value-based centrality has been via Monte Carlo simulations which are computationally expensive and not guaranteed to give an exact answer. Against this background, this paper presents the first study of the computational aspects of the Shapley value for network centralities. Specifically, we develop exact analytical formulae for Shapley value-based centrality in both weighted and unweighted networks and develop efficient (polynomial time) and exact algorithms based on them. We empirically evaluate these algorithms on two real-life examples (an infrastructure network representing the topology of the Western States Power Grid and a collaboration network from the field of astrophysics) and demonstrate that they deliver significant speedups over the Monte Carlo approach. For instance, in the case of unweighted networks our algorithms are able to return the exact solution about 1600 times faster than the Monte Carlo approximation, even if we allow for a generous 10% error margin for the latter method.

Efficient computation of the shapley value for centrality in networks

The Shapley Value is arguably the most important normative solution concept in coalitional games. One of its applications is in the domain of networks, where the Shapley Value is used to measure the relative importance of individual nodes. This measure, which is called node centrality, is of paramount significance in many real-world application domains including social and organisational networks, biological networks, communication networks and the internet. Whereas computational aspects of the Shapley Value have been analyzed in the context of conventional coalitional games, this paper presents the first such study of the Shapley Value for network centrality. Our results demonstrate that this particular application of the Shapley Value presents unique opportunities for efficiency gains, which we exploit to develop exact analytical formulas for Shapley Value based centrality computation in both weighted and unweighted networks. These formulas not only yield efficient (polynomial time) and error-free algorithms for computing node centralities, but their surprisingly simple closed form expressions also offer intuition into why certain nodes are relatively more important to a network.

SAMURAI: An accurate method for modelling and simulating non-stationary Random Telegraph Noise in SRAMs

In latest CMOS technologies, Random Telegraph Noise (RTN) has emerged as an important challenge for SRAM design. Due to rapidly shrinking device sizes and heightened variability, analytical approaches are no longer applicable for characterising the circuit-level impact of non-stationary RTN. Accordingly, this paper presents SAMURAI, a computational method for accurate, trap-level, non-stationary analysis of RTN in SRAMs. The core of SAMURAI is a technique called Markov Uniformisation, which extends stochastic simulation ideas from the biological community and applies them to generate realistic traces of non-stationary RTN in SRAM cells. To the best of our knowledge, SAMURAI is the first computational approach that employs detailed trap-level stochastic RTN generation models to obtain accurate traces of non-stationary RTN at the circuit level. We have also developed a methodology that integrates SAMURAI and SPICE to achieve a simulation-driven approach to RTN characterisation in SRAM cells under (a) arbitrary trap populations, and (b) arbitrarily time-varying bias conditions. Our implementation of this methodology demonstrates that SAMURAI is capable of accurately predicting non-stationary RTN effects such as write errors in SRAM cells.

MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs

With aggressive technology scaling and heightened variability, SRAMs and DRAMs have become vulnerable to Random Telegraph Noise (RTN). The bias-dependent, random temporal nature of RTN presents significant challenges to understanding its effects on circuits. In this paper, we propose MUSTARD, a technique and tool for predicting the impact of RTN on SRAMs/DRAMs in the presence of variability. MUSTARD enables accurate, non-stationary, two-way-coupled, discrete stochastic RTN simulation seamlessly integrated with deterministic, continuous circuit simulation. Using MUSTARD, we are able to predict experimentally observed RTNinduced failures in SRAMs, and generate statistical characterisations of bit errors in SRAMs and DRAMs. We also present MUSTARD-generated results showing the effect of RTN on DRAM retention times.

Accurate Prediction of Random Telegraph Noise Effects in SRAMs and DRAMs

With aggressive technology scaling and heightened variability, circuits such as SRAMs and DRAMs have become vulnerable to random telegraph noise (RTN). The bias dependence (i.e., non-stationarity), bi-directional coupling, and high inter-device variability of RTN present significant challenges to understanding its circuit-level effects. In this paper, we present two computer-aided design (CAD) tools, SAMURAI and MUSTARD, for accurately estimating the impact of non-stationary RTN on SRAMs and DRAMs. While traditional (stationary) analysis is often overly pessimistic (e.g., it overestimates RTN-induced SRAM failure rates), the predictions made by SAMURAI and MUSTARD are more reliable by virtue of non-stationary analysis.

MAPP: A platform for prototyping algorithms and models quickly and easily

The lack of a convenient yet powerful platform for prototyping simulation algorithms and mathematical models has long hindered research and collaboration in continuous-time (CT) simulation and modelling. We present the Berkeley Model and Algorithm Prototyping Platform (MAPP), which aims to make such prototyping and evaluation fast and easy. A key feature of MAPP is modular code structuring, the design of which is strongly influenced by modern, DAE-based formulations for system equations and algorithms. This internal code structuring, which differs markedly from that of Berkeley SPICE and related simulators, enables users to add new simulation algorithms with only minimal knowledge of device models, and vice-versa. Another key feature of MAPP is that it is designed from the ground up to support modelling and simulation multi-physics systems. We illustrate MAPPs implementation of devices and algorithms and present two samples of its use. MAPP has been released as open source under the GNU Public License.

Poster: MAPP: The Berkeley Model and Algorithm Prototyping Platform

We present the Berkeley Model and Algorithm Prototyping Platform (MAPP), a MATLAB®-based framework for conveniently and quickly prototyping device compact models and simulation algorithms. MAPPs internal code structuring, which differs markedly from that of Berkeley SPICE and related simulators, allows users to add new devices with only minimal knowledge of simulation algorithms, and vice-versa. We describe MAPPs structuring and provide an overview of its capabilities. MAPP is available as open source under the GNU Public License.

A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems

The design of a communications system is typically most effective only when each of its components can be accurately represented by a discrete, symbolic behavioural abstraction. Such abstractions, in addition to providing valuable design intuition, also enable highly efficient and scalable system-level simulation. However, given a SPICE-level description for a subsystem such as a latch, it is a challenge to come up with a discrete, symbol-level abstraction that accurately captures its continuous-time dynamics. Indeed, the manual construction of such an abstraction requires deep knowledge and understanding of the operation of the module in question; moreover, it is very time-consuming, tedious, error-prone and not easily scalable to larger designs. In recent work [1], we adapted methods from computational learning theory to develop an automated technique, DAE2FSM, that produces binary finite state machine (FSM) abstractions of non-linear analog/mixed-signal (AMS) circuits. In the present paper, we demonstrate the application of the DAE2FSM technique to automatically derive FSM abstractions for a mixed-signal communications circuit component, namely a current mode latch (CML) designed in IBMs 90nm LP process technology. We show that the FSMs learned by DAE2FSM not only capture the essence of the latchs behaviour during normal conditions, but also faithfully mimic its behaviour under adverse operating conditions (e.g., under lowered supply voltages). Moreover, in addition to a stand-alone CML, we also generate FSMs for cascades of two and three latches (such topologies are used in the design of power-efficient, bit-error optimised analog-to-digital converters). In spite of the inherent non-linearity of such systems, and in spite of the pronounced “analog-ness” of the waveforms in question, our FSM abstractions are able to produce discrete-time symbol sequences that closely match the data points obtained by sampling from continuous-time SPICE simulations.