Katarina Paulsson

Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs

The exploitation of dynamic and partial hardware reconfiguration on FPGAs is currently being investigated in various research projects, dealing with systems for space applications to automotive and masurement applications. Despite challenges such as a complicated design flow, dynamic reconfigurable systems offer advantages in terms of flexibility and performance. Unfortunately only few kinds of commercial architectures support dynamic and partial reconfiuration, which has lead to Virtex II / IV being main target architectures for this kind of systems. Additionally, the Xilinx Spartan III architecture is dynamically and partially reconfigurable with some limitations, one of them being the lack of an internal configuration port. The Virtex II / IV and V architectures all include the ICAP port, which allows a system to reconfigure itself during run-time without additional external components. Until now, this was not possible on the Spartan III architecture. This paper presents the implementation of a virtual internal configuration port for the Spartan III family of FPGAs. The configuration port was implemented for a hardware reconfigurable measurement system, which is implemented on a Spartan III FPGA due to its cost-and power optimized characteristics.

Parallel and flexible multiprocessor system-on-chip for adaptive automotive applications based on Xilinx MicroBlaze soft-cores

Xilinx Virtex FPGAs offer the possibility of dynamic and partial run-time reconfiguration. When designing a system that includes this feature it has to be made sure, that no signal lines cross the border to other reconfigurable regions. The complex modular design flow to generate partial bitstreams and the need of macros for physical interconnection of IP-Cores causes the necessity to investigate in alternatives. This paper describes the design and implementation of a software reconfigurable multiprocessor system, based on Xilinx MicroBlaze softcore processors. A real application in the automotive domain implemented on a Xilinx Virtex-II 3000 FPGA is used to present results.

Strategies to On- Line Failure Recovery in Self- Adaptive Systems based on Dynamic and Partial Reconfiguration

With the high complexity of future system-on-chips, many aspects such as synchronization, system control and system test and validation will be difficult to manage. Clock signals stretching over the complete die suffers from delays and cause synchronization problems, a centralized system control becomes a bottle neck and the high number of system components causes further problems when verifying the system functional correctness. Self-adaptive systems are an important field of research in order to find solutions to these problems. In this paper, a concept for self-recovery from behavioural failures is presented. The proposed methods are based on earlier work in this area which exploits dynamic and partial hardware reconfiguration. Hardware reconfiguration is an important feature in self-adaptive systems since it offers a higher degree of freedom, and in this case it also offers the possibility for a system to recover from a failure during run-time

Methods for run-time failure recognition and recovery in dynamic and partial reconfigurable systems based on Xilinx Virtex-II Pro FPGAs

The rapid development of hardware/software and microelectronic technology enables the realization of more complex systems with new characteristics. These characteristics could lead to further advances in electronic measurement-, control- and regulation systems. The industrial demands of future electronic systems rely on systems to be fault-tolerant, since the complexity increased to the point where it is impossible to detect all errors during the design phase. The ability for a system to recover from a failure requires that incorrect system operation can be detected and analysed during run-time. To achieve this, methods for performing tests of functionalities and components dynamically must be incorporated in the system behaviour during the design phase. This paper presents methods for efficient on-line failure detection, integrated in a reconfigurable system for execution and test of multiple automotive inner cabin functions. These methods also allow a certain degree of failure recovery, and even make it possible for a system to heal itself from more advanced faults. By exploiting the ability of dynamic and partial hardware reconfiguration, the monitoring can also be performed with less hardware overhead since the monitoring functionalities are configured only when they are required.

On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives

The flexibility of reconfigurable hardware can be exploited to adapt to requirements of applications while run-time. Hardware described functions can be configured dynamically when required, which leads to better usage of chip resources due to reduction of chip area and therefore reduced power consumption. Unfortunately the many restrictions of available run-time reconfigurable hardware architectures has until now limited the integration of such systems in real applications. Also, the high power consumption of reconfigurable architectures makes them suitable for mostly very high performance requiring applications such as signal processing tasks or multimedia applications. In this paper a method for 2D reconfiguration is described, which also enables on-line routing of communication primitives. In order to decrease the power consumption, we also propose a method for adapting signal routing according to power and performance. We demonstrate that there is a trade-off between the power and performance of on-chip signal lines, which can be exploited for on-line adaptation.

Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs

Field programmable gate arrays, FPGAs, are increasingly often applied in various industrial applications as well as investigated in different research projects. Due to the possibility for performing parallel computations, this kind of hardware architecture is especially interesting for high-performance applications. Dynamic and partial hardware reconfiguration, which is provided by several FPGA families such as the Xilinx Spartan 3 and Virtex 2/4 families, further increases the flexibility of these architectures. The Spartan 3 family was a less attractive choice for performing dynamic and partial reconfiguration due to the lack of an internal configuration port. However, a virtual internal configuration port, JCAP, has previously been realized by using the external JTAG interface. This paper presents an approach for internal configuration readback for failure detection and task migration by extending the JCAP core functionality. The paper also presents the first results from implementing self-reconfiguration over JCAP.

Data path driven waveform-like reconfiguration

The Xilinx Virtex FPGA family provides the capability to perform dynamic partial hardware reconfiguration (DPR). This implies that parts of the system can by dynamically reprogrammed while the rest of the system components continue their execution without being interrupted. Such reconfigurable FPGA systems are becoming more and more common for applications that require a high degree of run-time flexibility. One major research task in this area is to decrease the overhead caused by the reconfiguration duration. This can be done by increasing the reconfiguration rate, which means increasing the system performance when performing the reconfiguration. This paper presents an alternative approach which aims at decreasing the influence of the reconfiguration, by carefully dividing the reconfigurable modules according to the specific data graph and to start processing the data while the following parts of the data graph are still being reconfigured. This prevents data from being stalled and waiting for the reconfiguration to complete. The suggested approach is referred to as waveform-like reconfiguration, since the data processing closely follows the reconfiguration process.

Cost-and power optimized FPGA based system integration: methodologies and integration of a low-power capacity-based measurement application on Xilinx FPGAs

The application of field programmable gate arrays (FPGAs) in low power and low cost industrial mass products has become an important issue for designers of electronic systems. The flexibility and performance offered by reconfigurable hardware architectures often stands in the opposite to increased power consumption in comparison to application specific integrated circuit (ASIC) solutions. By exploiting the flexibility of reconfigurable hardware architectures, e.g. the capability of run-time HW reconfiguration of some modern FPGA devices, power consumption of FPGA-based solutions can be further decreased. This paper presents an approach for cost- and power optimized system integration of a low-power capacity-based measurement system by exploiting the dynamic and partial reconfiguration capability of Xilinx FPGAs.

On-Line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project

The progress in hardware technologies for implementing portable, low power and low cost electronic systems for consumer products has been major the last years. The complexity of embedded systems will further increase at a rate which is not met by the development of advanced CAD tools for managing the large design space. This will likely lead to increased design problems regarding system implementation, test and verification. In the next 15-20 years, it is likely that the consumer products are based on computing devices which are grouped together in networks including thousands or even millions of nodes. The /ETHER project deals with managing the complexity of such systems based on emerging technologies for future applications. This paper presents how the design complexity can be managed at the hardware level by integrating self-adaptive characteristics, and how the trade-off in performance and flexibility can be optimized to fulfill all application requirements while reducing the design complexity.

Exploitation of dynamic and partial hardware reconfiguration for on-line power/performance optimization

This paper presents the results from research work done in the field of reconfigurable architectures and systems. Dynamic and partial reconfiguration has mainly been investigated as a way to configure functionalities in hardware on-demand, controlled either by the user or by the system itself. This paper presents work that was aimed at applying hardware reconfiguration even for run-time adaptation of functional implementation in order to enable self-optimization of power and performance according to the run-time specific requirements of the application.