Katsuhiko Suyama

GaAs MOSFET High-Speed Logic

Enhancement-mode GaAs MOSFET integrated logic shows superior potential for applications in low-power high-speed integrated circuits. The speed / power performance of this logic was investigated by using GaAs MOSFET ring oscillators, fabricated using a low-temperature plasma oxidation technique for gate insulation. With an enhancement-depletion (E/D)-type ring oscillator, a minimum propagation delay of 110 ps per gate is obtained, with a power/speed product of 2.0 pJ. With an enhancement-enhancement (E/E) type, a minimum power/speed product of 26 fJ is obtained, with a 385-ps delay. These performances are equal to or better than those of GaAs MESFET logic, after adjustments are made for gate size. With further refinements in device geometry and improvements in gate oxide, GaAs MOSFET logic will be of great use in high-speed very-large-scale integrated circuits.

An MSI GaAs Integrated Circuit Using Ti/W Silicide Gate Technology

Direct-coupled FET logic (DCFL) circuits with self-aligned enhancement/depletion GaAs MESFETs are the most promising candidate for developing GaAs MSI/LSI circuits. A 4×4-bit parallel multiplier was fabricated as a test vehicle to demonstrate high-speed low-power circuit performance. The circuit chip measures 1.5 mm ×1.3 mm in size and contains 168 NOR gates with 2 µm gate length enhancement/depletion FETs. To evaluate the operating speed, a full adder implemented ring oscillator was fabricated. The propagation delay per gate was in the range between 210 and 260 ps with a power dissipation of 0.36 mW/gate. 4×4-bit multiplication was performed in 3.7 ns, with a power dissipation of 97 mW at a supply voltage of 1.5 V.

Planar GaAs IC's Using Multiple Localized Ion-Implantation

The family of planar GaAs ICs has been developed by using a multiple localized ion-implantation technique. In order to show advantages of the multiple localized ion-implantation technique, 5-stage ring oscillators and binary frequency dividers have been fabricated using both multiple ion-implantation and ordinary single ion-implantation. A maximum counting frequency of 2.2 GHz for the divider was obtained from ICs fabricated using the multiple ion-implantation technique; on the other hand, 1.1 GHz was obtained when single ion-implantation was used. A 4-bit arithmetic and logic unit (ALU) has been fabricated to examine the adaptability of this planar ion-implantation technique to the GaAs LSI fabrication process.

C-Band 10 W Power GaAs MESFET with an Internal Matching Circuit

A 15,000 µm wide gate GaAs MESFET has been operated successfully by the introduction of a low pass filter type internal matching circuit at C-band frequencies. It has been found that the drain-source breakdown voltage depended on the shape of the inlaid n+ region under the drain electrode. The output power of the FET increased with drain bias voltage up to 18 V. Typical output characteristics of the fabricated FET are as follows: P_out=10.0 W, G_A=6.1 dB, η_add=32.4% at 4 GHz P_out=5.4 W, G_A=4.0 dB, η_add=14.9% at 6.5 GHz where Pout, GA, and ηadd are output power, associated gain and power added efficiency, respectively.

Low-Power, High-Speed Integrated Logic with GaAs MOSFET

The speed/power performance of GaAs MOSFET logic is firstly demonstrated by using GaAs MOSFET ring oscillators. The gate oxide is formed by directly oxidizing GaAs with a low-temperature plasma oxidation technique. The minimum propagation delay per gate is 110 ps, with the power/speed product of 2.0 pJ. The minimum power/speed product is 26 fJ, with the delay time of 385 ps. These performances are equal to or better than those of GaAs MESFET logic in spite of that the GaAs MOSFET integration is in the first stage of developments. With further refinements of device geometries and improvements in gate oxide, GaAs MOSFET logic may be great use in a field of high-speed, very large scale integrated circuit applications.