Katzalin Olcoz

A method for area estimation of data-path in high level synthesis

This paper describes a new method to estimate the area of data paths generated during a High Level Synthesis (HLS) process, when the information concerning the circuit is not yet complete. Our method is more accurate and considers more factors than those used by other HLS systems of which we are aware. Our main concern is the interconnection area, often neglected by HLS systems, which has a strong influence on the final circuit area being optimized, as well as a high dependency on the technology used and on the circuit area itself. Predicting the area of a design layout with accuracy is important because it allows one to foresee whether the design will satisfy the area constraints, and will lend the allocator towards the best design among several possibilities with guarantees. Our estimations of the final standard-cell layout area are similar, or even more accurate, than those obtained following methods used by low-level design systems, which have much more information available. Due to the performance penalty their relatively high complexity will produce, these methods are unusable in an HLS system exploring a wide design space. Our estimation, on the contrary, has a low complexity and can be repeated time and again as the HLS design space is searched.

Dynamic management of nursery space organization in generational collection

The use of automatic memory management in object-oriented languages like Java is becoming eagerly accepted due to its software engineering benefits, its reduction in programming time and safety aspects. Nevertheless, the complexity of garbage collection results in an important overhead for the virtual machine job. Until now, the strategies in garbage collection have focused in defining and fixing regions in the heap based in different approached and algorithms. Each of these strategies can beat the others depending on the data behavior of a specific application, but they fail to take advantage of the available resources for other cases. There is not a static solution to this problem. In this paper, we present and evaluate two dynamic strategies based in data lifetime that reallocate at run time the reserved space in the nursery of generational Appel collectors. The dynamic tuning of the reserved space produces a drastic reduction in the number of collections and the total collection time and has a clear effect in the final execution time.

Adaptive tuning of reserved space in an appel collector

The use of automatic memory management in object-oriented languages like Java is becoming widely accepted because of its software engineering benefits, its reduction of programming time and its safety aspects. Nevertheless, the complexity of garbage collection results in an important time cost for the virtual machine’s job. Until now, garbage collection strategies have focused on analyzing and adjusting regions in the heap based on different approaches and algorithms. Each strategy has its own distinct advantages over the others depending on the data behavior of a specific application, but none succeeds in taking advantage of all available resources for all application behaviors. In this paper, we present and evaluate two adaptive strategies based on data lifetime that reallocate at run time the reserved space in the nursery of generational Appel collectors. The adaptive tuning of reserved space produces a drastic reduction in the number of collections and the total collection time, and has a clear effect on the final execution time.

Memory power optimization of Java-based embedded systems exploiting garbage collection information

Nowadays, Java is used in all types of embedded devices. For these memory-constrained systems, the automatic dynamic memory manager (Garbage Collector or GC) has been always a key factor in terms of the Java Virtual Machine (JVM) performance. Moreover, in current embedded platforms, power consumption is becoming as important as performance. Thus, in this paper we present an exploration, from an energy viewpoint, of the different possibilities of memory hierarchies for high-performance embedded systems when used by state-of-the-art GCs. This is a starting point for a better understanding of the interactions between the Java applications, the memory hierarchy and the GC. Hence, we subsequently present two techniques to reduce energy consumption on Java-based embedded systems, based on exploiting GC information. The first technique uses GC execution behavior to reduce leakage energy consumption taking advantage of the low-power mode of actual multi-banked SDRAM memories and it is intended for generational collectors. This technique can achieve a reduction up to 50% of SDRAM memory leakage. The second technique involves the inclusion of a software-controlled (scratch-pad) memory that stores GC instructions under the JVM control to reduce the active energy consumption and also improve the performance of the target embedded system and it is aimed at all kind of garbage collectors. For this last technique we have experimented with two different approaches for selecting the GC code to be stored in the scratchpad memory: one static and one dynamic. Our experimental results show that the proposed dynamic scratchpad management approach for GCs enables up to 63% energy consumption reduction and 25% performance improvement during the collector phase, which means, in terms of JVM execution, a global reduction of 29% and 17% for energy and cycles, respectively. Overall, this work outlines that the key for an efficient low-power implementation of Java Virtual Machines for high-performance embedded systems is the synergy between the GC choice, the memory architecture tuning, and the inclusion of power management schemes controlled by the JVM, exploiting knowledge of the GC behavior.

Refactoring Conventional Task Schedulers to Exploit Asymmetric ARM big.LITTLE Architectures in Dense Linear Algebra

Dealing with asymmetry in the architecture opens a plethora of questions from the perspective of scheduling task-parallel applications for which there exist early ad-hoc strategies embedded into an asymmetry-conscious runtimes. In this paper we take a different path that addresses the complexity of the problem at the library level, via a few asymmetry-aware fundamental kernels, hiding the architecture heterogeneity from the task scheduler. For the specific domain of dense linear algebra, we show that this elegant solution delivers much higher performance than a naive approach based on an asymmetry-oblivious scheduler. Furthermore, this solution also outperforms an ad-hoc asymmetry-aware scheduler furnished with sophisticated scheduling techniques.

Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems

Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multiple applications that are dynamically launched by the user, which can produce very energy-hungry systems if the interactions between the applications and the garbage collectors (GCs) are not properly understood. In this paper we present a complete exploration, from an energy viewpoint, of the different possibilities of memory hierarchies for high-performance embedded systems when used by state-of-the-art GCs. Moreover, we explore the potential peformance improvement and energy reductions of using a scratchpad memory directed by the virtual machine to store critical code and data structures of the GCs; thus, enabling up to 40% performance improvements and 41% leakage reduction with respect to classical cache-based memory architectures. Our experimental results show that the key for an efficient low-power implementation of Java Virtual Machines (JVM) for high-performance embedded systems is the synergy between the GC choice, the memory architecture tuning, and the inclusion of power management schemes controlled by the JVM, exploiting knowledge of the used GC.

Unified data path allocation and BIST intrusion

This paper deals with an approach to the automatic synthesis of self-testable data paths. A self-testable data path contains some test registers that increase its area. Classical approaches synthesizing minimum area data paths and then adding minimum number of test registers to it do not lead to data paths with minimum global area. Testability consideration during synthesis makes design search more efficient and hence can possibly find self-testable data paths with minimum area. We present a model to evaluate the testability of data paths that is used when data path allocation is being done. Moreover, we propose some heuristics that guide the design space search during allocation, to save exploration time. When each allocation decision has to be made, an implementation alternative is chosen according to the area and testability increments that the alternative produces, so that the area is only increased when the testability gain is worth it.

Data path structures and heuristics for testable allocation in high level synthesis

Abstract This paper presents a new testable allocation scheme that has been included in a high level synthesis environment to enhance the testability of the circuits synthesized. Designs obtained have small area overheads and no delays in critical timing parts of the circuit thanks to the testable structure generated by the simultaneous optimization of testability and cost during the exploration of the design space. Some heuristics are introduced that reduce the search time with no space bounding.

Energy characterization of garbage collectors for dynamic applications on embedded systems

Modern embedded devices (e.g. PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multiple complex applications (e.g. 3D rendering applications) that are dynamically launched by the user, which can produce very energy-hungry systems if they are not properly designed. Therefore, it is crucial for new embedded devices a better understanding of the interactions between the applications and the garbage collectors to reduce their energy consumption and to extend their battery life. In this paper we present a complete study, from an energy viewpoint, of the different state-of-the-art garbage collectors mechanisms (e.g. mark-and-sweep, generational garbage collectors) for embedded systems. Our results show that traditional solutions of garbage collectors for Java-based systems do not seem to produce the lowest energy consumption solutions.

Revisiting conventional task schedulers to exploit asymmetry in multi-core architectures for dense linear algebra operations

Abstract Dealing with asymmetry in the architecture opens a plethora of questions related with the performance- and energy-efficient scheduling of task-parallel applications. While there exist early attempts to tackle this problem, for example via ad-hoc strategies embedded in a runtime framework, in this paper we take a different path, which consists in addressing the asymmetry at the library-level by developing a few asymmetry-aware fundamental kernels. The appealing consequence is that the architecture heterogeneity remains then hidden from the task scheduler. In order to illustrate the advantage of our approach, we employ two well-known matrix factorizations, key to the solution of dense linear systems of equations. From the perspective of the architecture, we consider two low-power processors, one of them equipped with ARM big.LITTLE technology; furthermore, we include in the study a different scenario, in which the asymmetry arises when the cores of an Intel Xeon server operate at two distinct frequencies. For the specific domain of dense linear algebra, we show that dealing with asymmetry at the library-level is not only possible but delivers higher performance than a naive approach based on an asymmetry-oblivious scheduler. Furthermore, this solution is also competitive in terms of performance compared with an ad-hoc asymmetry-aware scheduler furnished with sophisticated scheduling techniques.