Kaveh Hosseini

Observations Concerning the Generation of Spurious Tones in Digital Delta-Sigma Modulators Followed by a Memoryless Nonlinearity

In mixed-signal systems, nonlinear distortion due to nonideal analog circuitry can act on quantized digital sequences, giving rise to spurious tones. In this brief, generation of spurious tones in digital delta-sigma modulators, followed by memoryless nonlinearity, is investigated. Inherent modulator periodicity that persists even with the use of least-significant-bit dither is identified.

HK-EFM and HK-SQ-DDSM

In this chapter, we show how cycle length maximization through architecture modification can be applied to two important classes of multi-bit modulators, namely higher order Error Feedback Modulators (EFMs) and Single-Quantizer DDSMs (SQ-DDSMs).

DDSM and Applications

In this chapter, we review the principles of delta-sigma modulation. We classify Delta-Sigma Modulators (DSMs) based on the types of signals they process and describe applications for each. Digital DSMs (DDSM) are used in fractional-N frequency synthesizers and oversampling Digital-to-Analog Converters (DACs). We review the basic operation of a delta-sigma DAC. Then we give an introduction to fractional-N synthesizers and the use of delta-sigma modulation in these systems. We highlight the problem of spurious tones in DDSMs resulting from short cycle lengths and indicate how they degrade the performance of the synthesizers. The chapter provides Simulink models and Matlab code for MASH, Multi-bit EFM and multi-bit SQ DDSMs.

Conventional Techniques for Maximizing Cycle Lengths

In this chapter, we review conventional stochastic and deterministic techniques that guarantee long cycles. First we explain the dithering approach, which belongs to the class of stochastic techniques. Then, we explain two deterministic techniques, namely setting the internal registers to predefined initial values and using prime modulus quantizers. These techniques yield longer cycles and thereby reduce the undesirable tones in the spectrum that arise when the period of the quantization error signal is short.

Maximizing Cycle Lengths by Architecture Modification

In this chapter, we describe deterministic techniques for maximizing the cycle length by changing the architecture (rather than by setting initial conditions and/or input or by adding dither). We modify the conventional MASH DDSM and refer to the new maximum cycle length structure as HK-MASH. First, the modified first-order Error Feedback Modulator (EFM) is described. Then, the modified EFM is utilized in the HK-MASH DDSM. The spectral performance of second, third, and fourth order HK-MASH modulators with small and large accumulator word lengths is studied by simulation.