Kayhan M. İmre

Model-Driven Approach for Supporting the Mapping of Parallel Algorithms to Parallel Computing Platforms

The trend from single processor to parallel computer architectures has increased the importance of parallel computing. To support parallel computing it is important to map parallel algorithms to a computing platform that consists of multiple parallel processing nodes. In general different alternative mappings can be defined that perform differently with respect to the quality requirements for power consumption, efficiency and memory usage. The mapping process can be carried out manually for platforms with a limited number of processing nodes. However, for exascale computing in which hundreds of thousands of processing nodes are applied, the mapping process soon becomes intractable. To assist the parallel computing engineer we provide a model-driven approach to analyze, model, and select feasible mappings. We describe the developed toolset that implements the corresponding approach together with the required metamodels and model transformations. We illustrate our approach for the well-known complete exchange algorithm in parallel computing.

A parallel implementation of Strassen's matrix multiplication algorithm for wormhole-routed all-port 2D torus networks

A new parallel implementation of Strassen’s matrix multiplication algorithm is proposed for massively parallel supercomputers with 2D, all-port torus interconnection networks. The proposed algorithm employs a special conflict-free routing pattern for better scalability and is able to yield a performance rate very close to the theoretical bound for many practical network and matrix sizes. It effectively scales up to very large networks typically containing hundreds-of-thousands processors where petaflop or exaflop processing rates are sought.

Dual-mode routing approach for photonic network on chip platforms

In this paper, a dual-mode routing approach is proposed for routing messages in 2D photonic network on chip (NoC) platforms. The dual-mode routing approach is based on selecting exclusively one of two routing techniques for each stage of a parallel application. Depending on the data exchange requirements of a specific stage of an application, either a conventional per-message-based routing or a collective routing technique is selected, and the network on chip architecture is organized to support that selection. The network on chip architecture that we use is a two-dimensional torus topology built from novel

Deriving Feasible Deployment Alternatives for Parallel and Distributed Simulation Systems

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Scheduling computation and communication on a software-defined photonic Network-on-Chip architecture for high-performance real-time systems

8×8 non-blocking all-port photonic switches. The design of

Systematic approach for deriving feasible mappings of parallel algorithms to parallel computing platforms

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