Kazuhiro Ohba

A Novel Resistance Memory with High Scalability and Nanosecond Switching

We report a novel nonvolatile dual-layered electrolytic resistance memory composed of a conductive Cu ion activated layer and a thin insulator for the first time. An ON/OFF mechanism of this new type memory is postulated as follows: Cu ions pierce through the insulator layer by applied electric field, the ions form a Cu conductive bridge in the insulator layer, and this bridge dissolves back to the ion activated layer when the field is reversed. The 4 kbit memory array with 1T-1R cell structure was fabricated based on 180 nm CMOS process. Set/reset pulses were 5 ns, 110 muA and 1 ns, 125 muA, respectively. Those conditions provide large set/reset resistance ratio of over 2 orders of magnitude and satisfactory retention. Essential characteristics for high capacity memories including superb scalability down to 20 nmphi, sufficient endurance up to 107 cycles and preliminary data for 4-level memory are also presented. These characteristics promise the memory being the next generation high capacity nonvolatile memory even before the scaling limitation of flash memories is encountered.

Thermal activation effect on spin transfer switching in magnetic tunnel junctions

A calculation of the intrinsic spin transfer switching current Ic0 is realized in the magnetic tunnel junctions (MTJs). Ic0 is determined by the distribution of Ic in repeated measurements, assuming the linear decrease of the thermal stability by increasing the spin-polarized current. The spin transfer torque is found to be proportional to η(I)I with the applied current I and I-dependent spin polarization η(I). Even in case that I is limited less than Ic due to the tunnel barrier breakdown, Ic0 is calculated with an assisting external magnetic field and making better use of the magnetic phase diagram. In our MTJs, the average intrinsic switching current density was 6.4MA∕cm2.

Magnetoresistive random access memory operation error by thermally activated reversal (invited)

The reliability in magnetoresistive random access memory (MRAM) write operation was investigated for both toggle and asteroid memory chips developed with 0.18μm CMOS process. Thermally activated magnetization reversal, being the dominant origin of the intrinsic write error, was studied theoretically and experimentally. For asteroid MRAM, the bit line or word line disturbing error on half selected bits was proved to have significant effect on the write operation margin, even in the ideal case free from bit-to-bit switching field distribution and the hysteresis loop shift. For toggle MRAM, on the other hand, the dominant origin of the error occurs for selected bits, although its impact is much smaller than in the case of asteroid MRAM. As was expected from the estimation based on the single domain model, more than 10mA operation margin with the error rate of <10−9, which is sufficiently small for semiconductor IC memory, was achieved for the toggle MRAM.

MRAM with improved magnetic tunnel junction material

Summary form only given. Increasing output and decreasing switching field distribution are very important for the development of magnetic tunnel junction (MTJ) materials, in order to achieve a high capacity MRAM. We introduce an amorphous MTJ material with excellent characteristics, which is evaluated through the MRAM/MTJ test element groups (TEG) with a MOS circuit.

Visualization of Conductive Filament during Write and Erase Cycles on Nanometer-Scale ReRAM Achieved by In-Situ TEM

The paper shows clear evidence that in-situ transmission electron microscopy (TEM) can be used as a powerful tool to analyze ReRAM operation. Reproducible resistive switching of 100k cycles in 30- or 70-nm Cu-Te CBRAMs was achieved for the first time during in-situ TEM observation. A TEM sample of the CBRAM cells was processed by a focused ion beam method. The formation and rupture of a Cu filament was observed and analyzed in the TEM with energy dispersive x-ray (EDX) mapping. Since the overshoot current at the resistive switching was efficiently suppressed by a MOSFET placed in the TEM holder, stable and reproducible ReRAM switching operations were achieved in the TEM.

A cross point Cu-ReRAM with a novel OTS selector for storage class memory applications

This paper demonstrates a cross point Cu based Resistive Random Access Memory (Cu-ReRAM) technology suitable for Storage Class Memory (SCM) applications. Two key technologies have been developed for large capacity of 100Gb-class SCM with 100 ns program speed and 10M cycles of program endurance. One is tight resistance distributions of Cu-ReRAM by inserting a barrier layer to prevent excess intermixing. The other is a novel Boron and Carbon (BC) based Ovonic Threshold Switch (OTS) selector which meets requirements for large cross point arrays with low leakage current, low threshold voltage variability, and high endurance.