Kazumi Hirata
NEC
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Featured researches published by Kazumi Hirata.
custom integrated circuits conference | 1993
Michio Yotsuyanagi; Toshiyuki Etoh; Kazumi Hirata
A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 mu m CMOS technology. >
IEEE Journal of Solid-state Circuits | 1990
Masato Motomura; Jun Toyoura; Kazumi Hirata; Hideyuki Ooka; Hachiro Yamada; Tadayoshi Enomoto
A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI has been developed using a 0.8- mu m triple-layer-Al, CMOS fabrication technology. A 13.02*12.51-mm/sup 2/ chip contains a specially developed 160-kb content addressable memory (CAM) and cellular automation processor (CAP). A single DISP chip can store a maximum of 2048 words, and performs dictionary search in various search modes, including an approximate word search. The character input rate for the dictionary search operation is 33 million characters per second. The DISP typically consumes 800 mW at a supply voltage of 5 V. A high-speed, functional 50000 word dictionary search system can be built with 25 DISP chips arranged in parallel, to play an important role in natural language processing. >
international solid-state circuits conference | 1990
Masato Motomura; J. Toyoura; Kazumi Hirata; Hideyuki Ooka; Hachiro Yamada; Tadayoshi Enomoto
A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) design that makes it practical to construct a 50000-word dictionary search system using only 20 DISPs is discussed. Special features of the DISP are (1) an architecture that drastically increases capacity of the content addressable memory (CAM), which handles high-speed character searches; (2) logic that increases the speed of the cellular automation processor (CAP), which conducts word searches; (3) architecture for reducing the size of CAP hardware. The fabrication technology employed was CD.8 mu m, 3-AI-level CMOS.<<ETX>>
SID Symposium Digest of Technical Papers | 2002
Kazuhide Yoshinaga; Hiroyuki Sekine; Shinya Onda; Tetsushi Satoh; Kazumi Hirata; Yuko Satoh; Ken Ishikawa; Hiroshi Okumura; Kenji Sera; Fujio Okumura
A 0.9” XGA liquid crystal light valve with low temperature Poly-Si TFT has been developed by using a stacked capacitor structure. The stacked capacitor structure could reduce storage capacitor area because most of the capacitor area is located above the pixel components, such as bus-lines and TFTs. Therefore, this structure could obtain the required storage capacitance without decreasing aperture ratio. A high aperture ratio of 65% and a high contrast ratio of over 500:1 have been achieved with the fabricated light valve.
custom integrated circuits conference | 1992
Michio Yotsuyanagi; Toshiyuki Etoh; Kazumi Hirata
We have developed a single 5V, lobit, SOMsps pipelined CMOS A/D Converter (ADC) with internal Sample-andHold (S/H) circuits. The ADC features a newly developed S/H circuit with an 80dB 300MHz operational amplifier (op. amp.), three-stage pipelined 4bit-flash-ADCs with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new ADC was fabricated with 0.8 ,U m CMOS technology.
international solid-state circuits conference | 1996
Hideki Asada; Kazumi Hirata; Kazunori Ozawa; Kunio Nakamura; Hiroshi Tanabe; Kenji Sera; K. Hamada; K. Mochizuki; S. Ohi; S. Saitoh; Fujio Okumura; Setsuo Kaneko
The rapid progress of multimedia demands liquid crystal display (LCD) projectors that can display computer data, such as video-graphic arrays (VGA), super-video-graphic arrays (SVGA), extended-graphic arrays (XGA) and super-extended-graphic arrays (SXGA). One of the major challenges for poly-Si TFT drivers in such multi-scan LCDs is displaying as black in the peripheral region around the picture during a blanking period. Using conventional shift register driver circuits, the scanning speed in the up-and-down no-picture region is too high for pixel TFTs to write signals for black. Although decoder driver circuits for multi-scan operation have been introduced into an HDTV poly-Si TFT-LCD, they require many address signals and logic gates. These increase circuit area and thereby decrease the manufacturing yields. Poly-Si TFT drivers use a combination of bi-directional shift registers and decoder circuits to solve the above problems for a 2.7 in, 1.3 Mpixel TFT LCD light valve.
Archive | 1998
Kazumi Hirata
Archive | 2004
Kazumi Hirata
Archive | 1996
Hideki Asada; Kazumi Hirata; Kazunori Ozawa; Kenichi Nakamura; Hiroshi Tanabe; Kenji Sera; Koji Hamada; Kazuo Mochizuki; Susumu Ohi; Shuichi Saitoh; Setsuo Kaneko
電子情報通信学会秋季大会講演論文集 | 1994
Fujio Okumura; Hideki Asada; Kenji Sera; Kazumi Hirata; Keiji Kurakagi; Yoshihiko Hirai; Setsuo Kaneko