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Dive into the research topics where Kazumitsu Nakamura is active.

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Featured researches published by Kazumitsu Nakamura.


Photomask and next-generation lithography mask technology. Conference | 2003

Arbitrary pattern fabrication with a LCD reticle-free exposure method

Tatsuo Morimoto; Kazumitsu Nakamura; Hiroshi Kubota; Akira Nakada; Takayuki Akamichi; Tsuneo Inokuchi; Kouji Kosaka

We describe a newly developed technique that uses optical projection lithography with a liquid crystal display (LCD) in place of a conventional reticle, in order to minimize turn-around-time and production cost. Circuit pattern data, generated by a computer aided design (CAD) system, is transferred directly to a control computer. The control computer converts the data into an equivalent dot matrix representation of the design for use on a LCD. The LCD is placed in a conventional optical stepper. One feature of this system is the simplicity of the data management scheme which permits the data to be handled by a computer file directly; without any of the manual assistance normally needed in conventional reticle fabrication. It is a very convenient method to reverse reticle tone by changing the LCD mode; easy compared to a conventional reticle manufacturing process. The minimum resolution of this proposed system is very similar to conventional systems that use optical reticles. We have demonstrated that this LCD Reticle-Free Exposure Method has the potential of replacing conventional reticles in optical stepper lithography. This method is applicable for manufacturing devices with relatively large fabrication rules and low production quantities, such as System-in-Package applications.


Photomask and next-generation lithography mask technology. Conference | 2002

Development of reticle-free exposure method with LCD projection image

Kazumitsu Nakamura; Hiroshi Kubota; Akira Nakada; Tsuneo Inokuchi; Kouji Kosaka

Liquid crystal display (LCD) in place of the conventional reticles for optical projection lithography is proposed, in order to minimize the turn-around-time and production cost. The transmittance ratio between the two modes of the LCD, such as transparent and opaque ones, is approximately a several dozen depending on the wave length of the light source. In this study, the Nikon g-line stepper was modified to apply the LCD on its reticle stage. The minimum resolution of this proposal projection system is quite similar to the one of the conventional reticle method. The exposure time is approximately 10 times longer compared to the conventional method. It has been proven that the LCD has the potential to be replaced for the conventional reticles in the optical stepper lithography that is applicable for devices with relatively large fabrication rules and low production amount.


Journal of Vacuum Science & Technology B | 1989

Investigation of the charging effect on thin SiO2 layers with the electron beam lithography system

Hiroyuki Itoh; Kazumitsu Nakamura; Hajime Hayakawa

The charging problem of a dielectric layer during direct exposure with an electron beam lithography system is investigated. Electron beam irradiation on a wafer with a dielectric layer such as SiO2 often causes charge buildup. This excessive accumulation of charge on the sample disturbs placement accuracy, and results in overlay errors. In order to analyze this charging problem, a metrology software package is used to measure the placement error of the exposed patterns on a target plane. Tested sample wafers are deposited with 0.2–1.5 μm SiO2, and then coated with 1 μm resist for exposure. To evaluate the charging dependence on electron beam current, a variable‐shaped electron beam lithography system which can easily change beam current is used. The results indicate that nongrounding 0.2 and 0.5 μm SiO2 do not show charge‐induced placement errors while 1 and 1.5 μm SiO2 show a definite placement error due to charging. On 1.5 μm Sio2 results indicate an electrostatic breakdown of SiO2, and no charging erro...


Journal of Vacuum Science & Technology B | 1991

Charging effects on trilevel resist and metal layer in electron‐beam lithography

Hiroyuki Itoh; Kazumitsu Nakamura; Hajime Hayakawa

Charging effects of trilevel resist on a W layer have been investigated with an electron beam lithography system. The tungsten layer was deposited before the resist and the charge‐induced beam deflections were measured for several thick W layers. A test pattern was employed consisting of an array 21×21 cross marks in a 3 mm field. The charging effects show different dependencies on W thickness between 20 and 30 keV because of the W backscattering. To evaluate the correlation between the charging and the backscattering process in W and trilevel resist, reflected electron signals were detected from the developed resist marks. The resist mark signal has a double sloped inverse peak characteristic due to backscattering from the W layer and absorption by the resist mark. As a result, the charge‐induced beam deflections and the intensity of backscattered electrons are increased in proportion to W thickness. The authors will discuss the electron distribution caused by the electron beam and sample material intera...


Journal of Vacuum Science & Technology B | 1990

Charging effects on trilevel resist with an e‐beam lithography system

Hiroyuki Itoh; Kazumitsu Nakamura; Hajime Hayakawa

The charging effect on a trilevel resist system was investigated with a variable‐shaped electron beam (e‐beam) lithography system. A test pattern which consists of two‐dimensionally arrayed marks was exposed on the trilevel resist and measured by the e‐beam. A method evaluating the correlation of repetitive measurement errors due to charging has been developed. This evaluation method was characterized such that the repetitive measurement and charging process occurred simultaneously without a conductive coating on the resist. The evaluation method of the charging process at 20 and 30 kV is demonstrated in this article. The resist result is different from that of silicon dioxide, and these phenomena are discussed together with the associated discharging processes.


Journal of Vacuum Science & Technology B | 1985

A high speed, high precision electron beam lithography system (system design)

Kazumitsu Nakamura; Yoshio Sakitani; T. Konishi; Tsutomu Komoda; Norio Saitou; K. Sugawara

A variably shaped electron beam lithography system HL‐600 has been developed for use in a semiconductor factory. HL‐600 was for high throughput. It is capable of direct wafer writing at high speed and also capable of mask writing at high accuracy. A very high speed beam control circuit has been developed. The pattern data were decomposed through the pipeline digital circuit. The settling time of the DA converter was shortened to 100 ns at full scale. An automated loader and wafer prealigner have been developed minimizing operator intervention. The specially designed computer and software system allow background processing pattern data during exposure. One of the most distinctive features of HL‐600 is the mode changing function. The large deflection mode guarantees writing of ten 4‐in. wafers per hour and the small deflection mode can accurately write submicron patterns. The mode change can be carried out immediately without special adjustment. This paper describes the system configuration in detail.


Japanese Journal of Applied Physics | 1974

In-Depth Analysis in Selected Area with Ion Microprobe Analyzer

Hifumi Tamura; Toshio Kondo; Ichiro Kanomata; Kazumitsu Nakamura; Yasuo Nakajima

In-Depth analysis is one of the most important application fields of ion microprobe analyzer. Various attempts have been already made and some of them have been used in practical applications. Conventional in-depth analysis includes the following problems. 1) In-depth analysis of a selected microscopic area. 2) In-depth analysis of thin surface layers. In this paper, the new technique to solve these problems are discussed. With reference to item 1), scan-stop method is developed. With reference to item 2), cancellation of the secondary ion yield change due to the transformed surface layers is achieved by taking a ratio of the specific ion current to total ion current.


Japanese Journal of Applied Physics | 1992

Error Analysis in Electron Beam Lithography System -Thermal Effects on Positioning Accuracy-

Hiroya Ohta; Takashi Matsuzaka; Norio Saitou; Katsuhiro Kawasaki; Kazumitsu Nakamura; Toshihiko Kohno; Morihisa Hoga

Thermal effects on positioning accuracy in an electron beam lithography system have been evaluated. In order to make 5X reticles for 0.3-µm ULSIs, positioning accuracy as small as 0.06 µm is required. Thermal effects are significant problems in achieving highly accurate reticle judging from positioning error analysis. In this study, internal thermal effects were investigated; these were (1) heating by electron beam illumination and (2) stage friction with step-and-repeat movement. As a result, the positioning error due to electron beam illumination is negligibly small compared with 0.06 µm and the stage temperature fluctuation must be controlled within 0.07°C to maintain a positioning error within 0.06 µm. Furthermore, internal thermal effects of the system could be fatal in next-generation electron beam lithography systems without improvement of materials and systems.


Japanese Journal of Applied Physics | 1976

Detection of SiO2- Ions from SiO2-Si Interface by Means of SIMS

Kazumitsu Nakamura; Hiroshi Hirose; Atsushi Shibata; Hifumi Tamura

Analytical conditions for sensitive detection of molecular ions are examined using thin oxide films grown naturally in air on silicon single crystal surfaces. This is carried out to clarify the behavior of these ions in SIMS. It is found that molecular ions can be detected more sensitively under the condition of the low energy primary ion beam incident at large angles. Secondary molecular ions have energies several electron volts lower than elemental secondary ions. SiO2-, and SiO3-, ions are hardly detected in 1500 ? thick CVD oxide layers, but are sensitively detected at the SiO2-Si interface and also in naturally oxidized layers. This result suggests that the chemical composition of the CVD oxide interface is similar to that of the natural oxide on silicon single crystals.


Japanese Journal of Applied Physics | 2005

Design and Fabrication of MOS Device Circuits with Reticle-Free Exposure Method

Katsuhiko Wakasugi; Satoshi Wakimoto; Akira Nakada; Ichiro Ohshima; Hiroshi Kubota; Kazumitsu Nakamura

An arbitrary pattern exposure method employing a liquid crystal display (LCD) for the formation of projection images has been applied to the design and fabrication of metal oxide semiconductor (MOS) devices and circuits. In this process, a transparent-type LCD with 1024×768 pixels and a g-line stepper were used. To realize the global pattern alignment on the stepper, we newly arranged an LCD reticle fitting the LCD on a quartz reticle which has a conventional alignment mark suitable for the stepper, in place of a conventional glass reticle. The MOS devices has been newly designed and fabricated with four layers in order to evaluate this new lithography concept. It has been confirmed that the n-MOS device can be correctly fabricated by this concept with reducing the manufacturing time. From the results, it is convinced that this method has the potential for replacing conventional glass reticles, particularly in the trial stage of device development.

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