Kazunobu Maeshige

Functional design of a pulsed two-frequency capacitively coupled plasma in CF4/Ar for SiO2 etching

A capacitively coupled plasma (CCP) with a different frequency source at each of two parallel plates is a powerful tool for SiO2 etching. A time modulation of two-frequency CCP by a pulsed-power operation will be one of the practical solutions in the next generation of etchers, and will allow charging-free plasma processes for high-aspect-ratio holes or trench etching. We numerically predict the structure and functions of a pulsed two-frequency CCP in CF4(5%)/Ar, and discuss its ability to generate charge-free plasma processes. We also investigate the functional separation between plasma production by very high frequency (100 MHz) and bias voltage application by low frequency (1 MHz). Alternate injections of high-energy positive and negative ions are predicted during the off-phase of a pulsed two-frequency CCP.

Effect of aspect ratio on topographic dependent charging in oxide etching

Consideration is given to a wall conductance inside a trench in SiO2 exposed by plasma etching in order to predict the wall surface charging as a function of the aspect ratio. With a lack of surface conductance, physical and electrical etch stops occur in SiO2 trench etching at high aspect ratios due to the difference of the velocity distribution between the electrons and the positive ions incident on the wafer. The sensitivity to the aspect ratio of the bottom charging potential decreases with the increasing surface electron conductance. The wall potential in the trench exposed to plasma etching in a pulsed operation is simulated in a simplified manner, and is predicted to be decreased by massive negative ions instead of electrons in the off-phase.

Prediction of a radial variation of plasma structure and ion distributions in the wafer interface in two-frequency capacitively coupled plasma

Two-frequency capacitively coupled plasmas (2f-CCP) are widely used as one of the powerful tools for SiO/sub 2/ etching. We numerically performed the design of SiO/sub 2/ etching by using VicAddress. Radial variation of plasma structure and ion distributions having a direct influence on etching were investigated in a 2f-CCP in CF/sub 4/(5%)/Ar, which consists both of a power source [very high frequency (VHF) 100 MHz] for high-density plasma production and a bias source (1 MHz) for the acceleration of ions toward the wafer. Degradation of the radial uniformity was observed near the wafer edge due to the distortion of surface potential mainly caused by the nonuniformity of electron flux at a wafer. Furthermore, we proposed a way of reducing the charge build-up inside the micro trench with the aid of negative charge injection by using a pulsed operation of VHF power source, especially at the low pressure condition.

Vertically integrated computer-aided design for device processing

The status of a series of numerical modelings of plasma etching processes is overviewed. Almost all models of low-temperature plasma, which were proposed in the mid- and late 1980s, are summarized, together with the boundary conditions that plasma processing faces. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench and electrical device damage during etching will make it possible to prepare a technology computer-aided design (CAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in ultra-large-scale integrated (ULSI) circuits in a closed integration system. Our basis for this study is the vertically integrated CAD for device processing (VicAddress), which the authors recently proposed. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.

Predictive study of a plasma structure and function in reactive ion etcher driven by very high frequency: Validity of an extended two-dimensional relaxation continuum model

The plasma structure and physical function of a narrow gap reactive ion etcher (RIE), consisting of capacitively coupled parallel plates driven at 100 MHz, have been predicted in a proper manner by an extended relaxation continuum model including gas flow and sputtered particle transport from the substrate. Monitoring the spatiotemporal excitation rate gives validity to the use of the continuum model even at 50 mTorr under higher power condition mainly maintained by an ionization multiplication of the secondary electrons ejected from the powered electrode by ion impacts. The plasma structures are testified by comparing the two-dimensional net excitation rate of Ar(3p5) with the experimental computerized tomography image. A nonvolatile particle transport successive to the physical etching on the substrate has been predicted in the RIE under a feed gas flow.

Future TCAD system for nanometer-scale-device manufacturing using plasma etching

The present stage of a series of numerical modelings of the plasma etching processes is overviewed. Physical, chemical and electrical linkage among modules describing low temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/trench, and electrical device damage during etching will make it possible to prepare a technology computer aided design (TCAD) for the practical purpose of prediction and designing the etching process. This system will also help to determine device arrangement and size in system on a chip (SoC) in a closed integration system. TCAD will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.

A series of modeling of plasma etching and damage reduction: vertically integrated computer aided design for device processing

Abstract The present stage of a series of numerical modelings of the plasma etching processes is overviewed. Physical, chemical and electrical linkage among modules describing low-temperature plasma structure/function in a reactor, the profile and local charging evolution in a hole/ trench, and electrical device damage during etching will make it possible to preparea technology computer aided design (TCAD) for the practical purpose of prediction and design of the etching process. This system will also help us to determine device arrangement and size in the system on a chip (SoC) in a closed integration system. Vertically integrated CAD for device processing (VicAddress) has been recently proposed by the authors. VicAddress will also provide a tool for discussing the etching processes between process engineers and device designers in the age of nanometer-scale device technology.