Kazuo Kyuma

Computer vision for computer games

The appeal of computer games may be enhanced by vision-based user inputs. The high speed and low cost requirements for near-term, mass-market game applications make system design challenging. The response time of the vision interface should be less than a video frame time and the interface should cost less than

Face recognition system using local autocorrelations and multiscale integration

50 U.S. We meet these constraints with algorithms tailored to particular hardware. We have developed a special detector, called the artificial retina chip, which allows for fast, on-chip image processing. We describe two algorithms, based on image moments and orientation histograms, which exploit the capabilities of the chip to provide interactive response to the players hand or body positions at 10 msec frame time and at low-cost. We show several possible game interactions.

Fiber-optic instrument for temperature measurement

In this paper we investigate the performance of a technique for face recognition based on the computation of 25 local autocorrelation coefficients. We use a large database of 11,600 frontal facial images of 116 persons, organized in training and test sets, for evaluation. Autocorrelation coefficients are computationally inexpensive, inherently shift-invariant and quite robust against changes in facial expression. We focus on the difficult problem of recognizing a large number of known human faces while rejecting other, unknown faces which lie quite close in pattern space. A multiresolution system achieves a recognition rate of 95%, while falsely accepting only 1.5% of unknown faces. It operates at a speed of about one face per second. Without rejection of unknown faces, we obtain a peak recognition rate of 99.9%. The good performance indicates that local autocorrelation coefficients have a surprisingly high information content.

Continuous wave operation of a surface‐emitting AlGaAs/GaAs multiquantum well distributed Bragg reflector laser

A practical fiber-optic measurement instrument for temperature was constructed consisting of a small sensor responding to optical absorption change in a semiconductor, and a unique signal processing system with two different-wavelength light emitting diodes (LEDs). The fiber-optic sensor with a semiconductor chip is quite small, very sensitive, highly reliable, and easy to manufacture at low cost. The most outstanding feature of this system is that it is free from optical-stray-loss. The accuracy of about \pm1\deg and the response time of about 2 s were obtained in the temperature range from -10°C to 300°C.

Narrow linewidth, single frequency semiconductor laser with a phase conjugate external cavity mirror

The first cw operation of an AlGaAs/GaAs distributed Bragg reflector laser was achieved at room temperature with a threshold current as low as 38 mA. Surface emission exceeding 4 mW was obtained with an external differential quantum efficiency of 9% and a beam divergence of 0.17°×10°. A two‐dimensional laser array with 3×4 gratings was also fabricated and an output power exceeding 500 mW was obtained under pulsed condition.

GaAs/AlGaAs Optical synaptic Interconnection Device for Neural Networks

We measure the spectral characteristics of an external cavity semiconductor laser which uses a phase conjugate mirror for its external reflection. This device has significant advantages over the conventional external cavity system owing to the self-aligning nature of the phase conjugate mirror. The fiber delay line self-heterodyne technique is used to measure the fundamental linewidth for single mode operation of this device. It shows the linewidth to be at least as narrow as the instrumental resolution of 100 kHz.

A 1 V 46 ns 16 Mb SOI-DRAM with body control technique

A GaAs/AlGaAs optical synaptic interconnection device for neural networks is reported for the first time to our knowledge. This device consists of a light-emitting-diode array, an interconnection matrix, and a photodiode array, which are integrated into a hybrid-layered structure on a GaAs substrate. The device structure and characteristics are reported in detail. The fabricated device can simulate a 32-neuron system. Experimental results of the Hopfield associative memory with three stored vectors are also described.

Demonstration of an all‐optical associative holographic memory

Low-voltage and low-power DRAMs of appropriate capacity are required for portable systems such as portable PCs and Personal Digital Assistants (PDAs). Though a 1.2 V 49 ns bulk-DRAM has been reported, still lower voltage operation is difficult for bulk-DRAMs, due to the back bias effect and large junction capacitance. SOI devices have several advantages over bulk devices, such as small subthreshold swing (S-factor), elimination of the back bias effect, and small junction capacitance. To utilize these advantages, many SOI-DRAM studies and proposals have been made. The basic operation of the SOI-DRAM at 2.3 V has been examined using an experimental 64 kb SOI-DRAM, and a 3 V 50 ns 16 Mb SOI-DRAM has been also reported. Here the authors present a 1 V 46 ns 16 Mb SOI-DRAM which uses a 0.5 /spl mu/m CMOS/SIMOX process. To accelerate low-voltage speed, a body-pulsed sense amplifier (BPS) and body-driven equalizer (BDEQ) are used. The conventional body-control technique uses partially-depleted (PD) transistors. In contrast, fully-depleted (FD) transistors are used to reduce leakage current in the off-state.

A 1.6 GB/s data-rate 1 Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture

We describe a new type of associative holographic memory and some related results. The memory can retrieve overlapping images which are stored in a volume hologram. The storage and retrieval of more than one image is demonstrated for the first time. The important role of thresholding in assuring ‘‘clean’’ retrieval is demonstrated.

Laser Doppler velocimeter with a novel optical fiber probe

This paper describes key technologies for a 1.6 GB/s high bandwidth 1 Gb synchronous DRAM (SDRAM). Its high data transfer rate and large memory capacity are intended for a unified memory system in which a single DRAM (array) is time-shared as both main memory and 3D graphics frame memory. 200 MHz operation is achieved by the hierarchical square-shaped memory block (SSMB) layout and the distributed bank (D-BANK) architecture. A built-in self-test (BIST) circuit with margin-test capability is included.