Kazuo Sakiyama

Low-Cost elliptic curve cryptography for wireless sensor networks

This work describes a low-cost Public-Key Cryptography (PKC) based solution for security services such as key-distribution and authentication as required for wireless sensor networks. We propose a custom hardware assisted approach to implement Elliptic Curve Cryptography (ECC) in order to obtain stronger cryptography as well as to minimize the power. Our compact and low-power ECC processor contains a Modular Arithmetic Logic Unit (MALU) for ECC field arithmetic. The best solution features 6718 gates for the MALU and control unit (data memory not included) in 0.13 μm CMOS technology over the field

Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2^n)

{mathbb{F}_{2^{131}}}

A Parallel Processing Hardware Architecture for Elliptic Curve Cryptosystems

, which provides a reasonable level of security for the time being. In this case the consumed power is less than 30 μW when operating frequency is 500 kHz.

Public-Key Cryptography on the Top of a Needle

This paper presents a reconfigurable curve-based cryptoprocessor that accelerates scalar multiplication of Elliptic Curve Cryptography (ECC) and HyperElliptic Curve Cryptography (HECC) of genus 2 over GF(2n). By allocating a copies of processing cores that embed reconfigurable Modular Arithmetic Logic Units (MALUs) over GF(2n), the scalar multiplication of ECC/HECC can be accelerated by exploiting Instruction-Level Parallelism (ILP). The supported field size can be arbitrary up to a(n + 1) - 1. The superscaling feature is facilitated by defining a single instruction that can be used for all field operations and point/divisor operations. In addition, the cryptoprocessor is fully programmable and it can handle various curve parameters and arbitrary irreducible polynomials. The cost, performance, and security trade-offs are thoroughly discussed for different hardware configurations and software programs. The synthesis results with a 0.13-mum CMOS technology show that the proposed reconfigurable cryptoprocessor runs at 292 MHz, whereas the field sizes can be supported up to 587 bits. The compact and fastest configuration of our design is also synthesized with a fixed field size and irreducible polynomial. The results show that the scalar multiplication of ECC over GF(2163) and HECC over GF(283) can be performed in 29 and 63 mus, respectively.

Montgomery Modular Multiplication Algorithm on Multi-Core Systems

We propose a parallel processing crypto-processor for elliptic curve cryptography (ECC) to speed up EC point multiplication. The processor consists of a controller that dynamically checks instruction-level parallelism (ILP) and multiple sets of modular arithmetic logic units accelerating modular operations. A case study of HW design with the proposed architecture shows that EC point multiplication over GF(p) and GF(2m) can be improved by a factor of 1.6 compared to the case of using single processing element

Tripartite modular multiplication

This work describes the smallest known hardware implementation for elliptic/hyperelliptic curve cryptography (ECC/HECC). We propose two solutions for public-key cryptography (PKC), which are based on arithmetic on elliptic/hyperelliptic curves. One solution relies on ECC over binary fields F2n where n is a composite number of the form 2p (p is a prime) and another on HECC on curves of genus 2 over F2p. This implies the same arithmetic unit for both cases which supports arithmetic in a field F2p. Our best solution that still results in a feasible performance features less than 5 kgates with an average power consumption smaller than 10 muW.

High-performance public-key cryptoprocessor for wireless mobile applications

In this paper, we investigate the efficient software implementations of theMontgomery modular multiplication algorithm on amulti-core system. AHW/SW co-design technique is used to find the efficient system architecture and the instruction scheduling method. We first implement the Montgomery modular multiplication on a multi-core systemwith general purpose cores. We then speed up it by adopting the Multiply-Accumulate (MAC) operation in each core. As a result, the performance can be improved by a factor of 1.53 and 2.15 when 256-bit and 1024-bit Montgomery modular multiplication being performed, respectively.

A compact and efficient fingerprint verification system for secure embedded devices

This paper presents a new modular multiplication algorithm that allows one to implement modular multiplications efficiently. It proposes a systematic approach for maximizing a level of parallelism when performing a modular multiplication. The proposed algorithm effectively integrates three different existing algorithms, a classical modular multiplication based on Barrett reduction, the modular multiplication with Montgomery reduction and the Karatsuba multiplication algorithms in order to reduce the computational complexity and increase the potential of parallel processing. The algorithm is suitable for both hardware implementations and software implementations in a multiprocessor environment. To show the effectiveness of the proposed algorithm, we implement several hardware modular multipliers and compare the area and performance results. We show that a modular multiplier using the proposed algorithm achieves a higher speed comparing to the modular multipliers based on the previously proposed algorithms.

Reconfigurable modular arithmetic logic unit supporting high-performance RSA and ECC over GF( p )

We present a high-speed public-key cryptoprocessor that exploits three-level parallelism in Elliptic Curve Cryptography (ECC) over GF(2n). The proposed cryptoprocessor employs a Parallelized Modular Arithmetic Logic Unit (P-MALU) that exploits two types of different parallelism for accelerating modular operations. The sequence of scalar multiplications is also accelerated by exploiting Instruction-Level Parallelism (ILP) and processing multiple P-MALU instructions in parallel. The system is programmable and hence independent of the type of the elliptic curves and scalar multiplication algorithms. The synthesis results show that scalar multiplication of ECC over GF(2163) on a generic curve can be computed in 20 and 16xa0μs respectively for the binary NAF (Non-Adjacent Form) and the Montgomery method. The performance canxa0be accelerated furthermore on a Koblitz curve and reach scalar multiplication of 12xa0μs with the TNAF (τ-adic NAF) method. This fast performance allows us to perform over 80,000 scalar multiplications per second and to enhance security in wireless mobile applications.

Superscalar coprocessor for high-speed curve-based cryptography

Creating a biometric verification system in a resource-constrained embedded environment is a challenging problem. This paper describes an efficient fingerprint verification module, which is part of an embedded device called ThumbPod. The whole fingerprint verification algorithm runs on a 50 MHz fixed-point processor. As the result of our SW/HW optimizations, we achieve 55.6% and 60.0% execution time reduction for the minutiae extraction and the matching, respectively, compared to a traditional implementation reference. The complete process finishes in less than 5 seconds.