Kazushi Kobayashi

Bus system for use with information processing apparatus

Multiprocessor system and interruption control device for controlling interruption requests between processors and peripheral devices in the multiprocessor system

Arithmetic-logic operation unit having high-order and low-order processing sections and selectors for control of carry flag transfer therebetween

Address bus control apparatus

Information processing apparatus with connection between memory and memory control unit

Address conversion apparatus accessible to both I/O devices and processor and having a reduced number of index buffers

Enhanced information processing system using cache memory indication during DMA accessing

Bus system for information processing system and method of controlling the same

Copyback memory system and cache memory controller which permits access while error recovery operations are performed

Multiple bus system using a data transfer unit