Kazushi Kodama

Analysis and Improvement of Retention Time of Memorized State of Metal-Ferroelectric-Insulator-Semiconductor Structure for Ferroelectric Gate FET Memory

Retention characteristics of metal-ferroelectric-insulator-semiconductor (MFIS) structures have been studied theoretically by considering effects of charge injections derived from the difference between leakage current densities in the ferroelectric and insulator layers. The calculated curves for time-dependent capacitance have shown good agreements with experimental results. The numerical results for the MFIS structure have indicated that excess current over a certain value through the ferroelectric and the insulator layers causes the retention time to rapidly degrade. An idea of inserting an insulator film between the metal and the ferroelectric layers in an MFIS has also been examined in order to cut down the currents through the ferroelectric layer. The calculations based on our model have found this metal-insulator-ferroelectric-insulator-semiconductor (M-I-FIS) structure to exhibit much longer retention time than the conventional MFIS.

Improved Retention Characteristics of Metal-Ferroelectric-Insulator-Semiconductor Structure Using a Post-Oxygen-Annealing Treatment

An oxygen-annealing process after SrBi2Ta2O9 (SBT) ferroelectric film deposition has effectively improved retention properties of the metal-ferroelectric-insulator-semiconductor (MFIS) structure for FET-type ferroelectric nonvolatile memory. The annealing treatment 1) reduces the surface roughness of the SBT film, 2) improves crystallinity, 3) effectively decreases the leakage current through the MFM structure, 4) increases the barrier height at the metal-ferroelectric interface, 5) decreases the carrier trap density in SBT film, and 6) improves the retained polarization of SBT film itself. Finally, the retention time of the memorized state in the MFIS diode was successfully increased to 2×104 s or more by the postannealing treatment.

Basic characteristics of metal-ferroelectric-insulator-semiconductor structure using a high-k PrOx insulator layer

A metal-ferroelectric [SrBi2Ta2O9 (SBT)]-high-k-insulator(PrOx)-semiconductor(Si) structure has been fabricated and evaluated as a key part of metal-ferroelectric-insulatorsemiconductor-field-effect-transistor MFIS-FET memory, aiming to improve the memory retention characteristics by increasing the dielectric constant in the insulator layer and suppressing the depolarization field in the SBT layer. A 20-nm PrOx film grown on Si(100) showed both a high e of about 12 and a low leakage current density of less than 1×10−8 A/cm2 at 1.5 MV/cm. A 400-nm SBT film prepared on PrOx/Si shows a preferentially oriented (105) crystalline structure, grain size of about 130 nm and surface roughness of 3.2 nm. A capacitance–voltage hysteresis is confirmed on the Pt/SBT/PrOx/Si diode with a memory window of 0.3 V at a sweep voltage width of 12 V. The memory retention time was about 1×104 s, comparable to the conventional Pt/SBT/SiOxNy(SiON)/Si. The gradual change of the capacitance indicates that some memory degradation me...

A Significant Improvement in Memory Retention of Metal-Ferroelectric-Insulator-Semiconductor Structure for One Transistor-Type Ferroelectric Memory by Rapid Thermal Annealing

A rapid thermal annealing (RTA) process has improved the crystallinity of the ferroelectric SrBi2Ta2O9 (SBT) thin film in metal-ferroelectric-insulator-semiconductor (MFIS) structures. The RTA temperature and time were in the ranges from 600 to 1000°C and 30 s to 1 min, respectively. X-ray diffraction (XRD) patterns showed clear preferential perovskite SBT(115) peaks in the temperature range. The RTA increases grain size to approximately 180 nm but markedly decreases surface roughness to approximately 5 nm due to having a shorter annealing time than the furnace annealing. Leakage current density through the MFIS is below 5×10-8 A/cm2, and is fairly reduced especially at the low electric field region as a result of the shorter RTA time. Finally, a very long retention time of 6×105 s (i.e., one week) was obtained by the RTA at 1000°C for 30 s. The extrapolated retention time from the data was about 3×107 s (i.e., one year).

Oxygen annealing effect of photoelectron spectra in SrBi2Ta2O9 film

Photoelectron spectra have been studied to clarify O-2-annealing effects on the band diagram of the metal-SrBi2Ta2O9 (SBT) junction and ionization energy of SBT films deposited by the pulsed laser, ...

Effect of leakage current through ferroelectric and insulator on retention characteristics of metal-ferroelectric-insulator-semiconductor structure

Abstract Retention characteristics of MFIS (metal-ferroelectric-insulator-semiconductor) structures have been investigated theoretically and experimentally. The simulated retention characteristics have indicated that reducing current through the ferroelectric layer is very effective to make the retention time long. In order to reduce the current through the ferroelectric layer, an MFIS with an improved ferroelectric layer and an M-I-FIS (metal-insulator-ferroelectric-insulator-semiconductor) have been investigated theoretically. Both of them have given good retention characteristics. Experimentally, retention characteristics of MFIS have been much improved by annealing, which is considered to suppress the current density in the ferroelectric layer, although those of M-I-FIS have been improved a little.

Electrical properties of Metal-Ferroelectric-Insulator- Semiconductor-FET using SrBi2Ta2O9 film prepared at low temperature by Pulsed Laser Deposition

Abstract We fabricated a Metal-Ferroelectric-Insulator-Semiconductor-FET with an SBT/SiON/Si gate structure, where SBT is prepared by Pulsed Laser Deposition at a low temperatue of 500°C and SiON is directly grown on Si in N2O gas at 970°C. A fabricated SBT/SiON/Si diode has an excellent interface between SiON and Si with interface stated density of about 3 × 1011 cm−2 eV−1 and a counterclockwise hysteresis with a large memory window of about 3.2 V. The corresponding MF(ON)S-FET has also a large memory window of about 3.1 V, subthreshold leakage of 10−9 to 10−8 A and an Id(ON) to Id(OFF) current ratio of about 4 orders of magnitude. The observed hysteresis in the MF(ON)S-FET is found to be originated from ferroelectric polarization reversal from the result of the sweep rate dependence of gate voltage from 0.2 V/s to 40 kV/s and of the relation between the memory window increase and applied gate voltage width, and the measured retention time of the MF(ON)S-FET is around 104 sec.

An analysis of effects of device structures on retention characteristics in MFIS structures

Retention characteristics of Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structures have been studied theoretically by considering currents through the ferroelectric and insulator layers. The simulations have successfully reproduced the memory retention curves, and agree well with experimentally obtained curves. The numerical results have indicated that a slight increase of Schottky barrier height of the ferroelectric layer provides sufficiently long retention time for practical use. The idea of inserting an insulator film between metal and ferroelectric layers has been also examined in order to cut off the currents through the ferroelectric layer. This Metal-Insulator-Ferroelectric-Insulator-Semiconductor (MIFIS) structure has been found to exhibit much longer retention time than the original MFIS.

Theoretical and Experimental Studies on Retention Characteristics of Metal-Ferroelectric-Insulator-Semiconductor and Metal-Insulator -Ferroelectric-Insulator-Semiconductor Structures

Retention characteristics of Metal-Ferroelectric-Insulator-Semiconductor(MFIS) and Metal-Insulator-Ferroelectric-Insulator-Semiconductor(M-I-FIS) structures have been investigated both theoretically and experimentally. The simulated time dependence of capacitance for the MFIS has indicated that reducing currents through the ferroelectric and the insulator layers improves the retention characteristics more effectively than choosing the insulators with larger dielectric constants. The M-I-FIS structure has been studied in order to reduce the charge injection between the metal and the ferroelectric layer in the MFIS. The simulations have indicated that the M-I-FIS can provide much longer retention time than the original MFIS, although the experimental retention time of the M-I-FIS have almost the same as that of the MFIS.