Kazushige Yamamoto

Voice-band signal processor

A voice-band signal processor uses a DSP to filter digital transmit and receive voice-band signals, and has oversampling D/A and A/D converters with a frequency converter to convert between the oversampling rate and the DSP rate. An interpolator converts the filtered receive voice-band signal to a pseudo-analog signal that can be sampled by a demodulator in synchronization with a regenerated receive sampling clock, thus enabling correct operation even when the transmit and receive sampling clock rates do not match. In addition, the voice-band signal processor contains a status register circuit connected to flag registers in the DSP, enabling a host computer to read and set flag values that control the operating mode of the voice-band signal processor. The voice-band signal processor can thus be switched between half duplex and full duplex operation, or between different bit rates.

A subscriber line interface processor for asynchronous transfer mode switching system

A subscriber line interface processor (A-LIP), which connects a conventional analog telephone line to a port on an asynchronous transfer mode (ATM) switching network through the contention control circuit, has been developed. The functions and circuit structure of the A-LIP chip designed to enhance the efficiency of ATM transmission, a divider added to the digital signal processor in a pipeline processing environment, and a cell data addressing scheme for transferring data between memory and input/output buffers without interfering with pipeline processing are described.<<ETX>>

A front-end processor for modems

The authors describe the front-end processor (FEP) which permits the construction of a multistandard modem system, incorporating the CCITT V.32 echo canceling scheme, using a general-purpose signal processor. The FEP is divided into a digital signal processing (DSP) block and an analog-digital/digital-analog conversion block. The DSP is designed to handle biquad filtering, tone generation, automatic gain control, call-progress-tone detection, and carrier detection. The multiplier, ALU (arithmetic and logic unit), and RAM are adapted to handle 22-bit data operation and to obtain high resolution and a 16-bit dynamic range operation in fixed-point calculations. The measured bit error rate of 14.4-kb/s trellis coding modem using the FEP is less than 10/sup -5/ at a signal-to-noise ratio of 27 dB under the US unconditioned 3002 line. The chip is fabricated in a 1.5- mu m double-poly double-metal CMOS process and designed using an automatic layout tool.<<ETX>>

An asynchronous FSK MODEM

A single chip, complete FSK MODEM, that can operate at 300b/s and is CCITT V.21 compatible, will be described. A 5μm double polysilicon gate CMOS process is used for the chip, which contains a flexible data terminal equipment interface circuit.