Kazuto Nishida

Reliability evaluation of ultra-thin CSP using new flip-chip bonding technology––double-sided CSP and single-sided CSP

Abstract A high-density packaging technology has been developed that uses new flip-chip bonding technology with a thin IC and a thin substrate. Numerical analysis with the finite element method as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided chip-size packages (CSPs) could be expressed using a normal stress value in thickness, which is computed by the IC thickness and substrate type and thickness. The dependency of the life in double-sided CSPs could be expressed using a shear stress value in the vertical cross section, which is computed in IC thickness and substrate type and thickness, respectively. Moreover, a double-sided flip-chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional CSP.

Reliability Analysis of ACF Interconnection Assembly Process Using FEM

Anisotropic conductive film (ACF) is commonly used as underfill for flip chip assembly. The present study focuses on elastic recovery and stress distribution along the interfaces of particle-pads and underfill-pads associated with heat or a mechanical loading. In the same manner as the experimental process for ACF assemblies, ACF interconnection is simulated using FEM. Firstly, the properties of the nickel were determined by fitting FEM to the experimental results. After that, the nickel properties are used for ACF interconnection analysis. We found that delamination may also occur at a three-joint interface of a particle, a pad and an underfill at the lowest temperature during a heat cycle.

Soldering Properties and Interfacial Microstructure of CSP Solder Joints with Lower Melting Lead-free Solder

In this paper we investigate the appropriate reflow profiles for simulated CSP solder joints using Sn-Ag-Bi-In solder, which has a lower melting point than Sn-Ag-Cu solder. We have examined the relationship between the interfacial microstructure and mechanical characteristics of Sn-Ag-Bi-In solder at the solder joints compared with those of Sn-Zn-Bi solder. When soldering Sn-3Ag-0.5Cu CSP balls on a Cu/Ni/Au pad, Sn-8Zn-3Bi showed high joint strength at 503 K or higher, whereas Sn-3.5Ag-0.5Bi-8In showed strength at the lower temperature of 493 K. This implies that Sn-Ag-Bi-In solder is more appropriate for soldering at lower temperatures. On the joint interface, a stratified Ni-Sn layer was formed when the Sn-3Ag-0.5Cu CSP ball was soldered on the Cu/Ni/Au phases are pad using Sn-3.5Ag-0.5Bi-8In at 483 ~ 493 K. At 503 K or higher, clumped (Cu,Ni)6Sn5 unevenly formed on the joint interface, resulting in lower strength. These results suggest the appropriate reflow thermal profile for Sn-3.5Ag-0.5Bi-8In sold...

Effects of Interfacial Microstructure on Strength of Solder Joint Using Sn-Ag-Bi-In Solder

In the present research a BGA (Ball Grid Array) type Sn-3Ag-0.5Cu solder ball was reflowed on Cu/Ni/Au pad using a Sn-3.5Ag-0.5Bi-8In solder or a Sn-8Zn-3Bi solder with varying reflow peak temperature and the interfacial microstructure and joint strength were evaluated. The strength of the Sn-3.5Ag-0.5Bi-8In solder joints reached the maximum value at reflow peak temperature of 483K to 493K and then decreased with increasing reflow temperature, whereas the Sn-8Zn-3Bi solder joints had high strength at the higher reflow peak temperature of 503K. In the Sn-3.5Ag-0.5Bi-8In solder joints, at a reflow peak temperature of 493K or less, a thin Ni-Sn type intermetallic layer formed at the interface between the solder and the pad. However at the higher reflow peak temperatures a clumpy (Cu, Ni)6 Sn5 phase locally formed on the Ni-Sn interfacial reaction layer. This is caused by Cu from melted Sn-Ag-Cu ball reacting to Ni and Sn in the interfacial region. The (Cu, Ni)6 Sn5 clumps increased with reflow peak temperature. Some void-like defects existed at the interface between the Ni-Sn layer and (Cu, Ni)6 Sn5 clumps. These defects can act as crack initiation sites and thereby cause the degradation of the joint strength. It is concluded from the results that when the Sn-3.5Ag-0.5Bi-8In solder is applied to reflow soldering of the packages having Sn-Ag-Cu solder bump on the Cu/Ni/Au pad, the reflow peak temperature should be controlled ranging from 483K to 493K. When the reflow peak temperature was over 493K, a holding of 20s at the peak temperature, which resulted in diminish the void-like defects at the interface between the Ni-Sn layer and the (Cu, Ni)6 Sn5 clumps, improved the joint strength.Copyright

A Thermo-Viscoelastic Analysis and Reliability Evaluation for a Single-Sided CSP

In the present paper, a reliability of a single-sided chip-size package (CSP) manufactured using a non-conductive adhesive stud bump direct interconnection method is investigated. The reliability of the CSP is closely related with normal stress between an IC chip and a gold bump. Total normal stress can be decomposed into two parts, deflection related and thermal expansion related. The deflection for a three-layered plate, which is taken into account viscoelastic properties for the resin-sealed sheet and the substrate, respectively, is calculated and compared with experimental results on the deflection of the single-sided CSP. A relationship between the normal stress and the curvature derived from deflection is deduced. Through the use of this relationship, the variation of normal stress with the heat cycle is obtained considering the viscoelastic properties of materials. Furthermore, a relaxation behavior for the thermal stress in the resin-sealed sheet between two rigid walls considering its viscoelastic property is investigated. Summing up normal stresses for each calculation yields the normal stress between the IC and the bump. A relationship between the normal stress and the life of single-sided CSP is investigated for heat cycle. The life in experiment can be explained by the relaxation in the normal stress and the amplitude of the normal stress.Copyright

Ultra-Thin and High-Density Packaging Using Both Sides Flip Chip Technology

We have developed a high-density packaging technology by using a thin IC and a thin substrate and bonding it by new flip chip technology. Numerical analysis with the finite element method (FEM) as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided CSP and both-sided CSP on the thickness of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively. Moreover, a both-sided flip chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional chip-size package (CSP).Copyright

Development of Film Module With Embedded Actives

Since electric products need more effective features in terms of being compact, small, thin and highly performant, a new concept to create the advanced JISSO is required. We have invented the film module manufacturing process, in which the semiconductor is embedded into the thermo-elastic film and wired directly to exposed bumps. In this device, the fundamental process which is the embedded semiconductor into the thermoplastic film PETG, has been developed. This process is essential for the embedded active components film. This technique can be applied to packaging, memory cards, smart cards, flexible multi layer film and so on. The embedding process has the following problems; 1) Stud bumps on the IC may not appear on the surface of the film, 2) Voids may appear in the film during a high temperature press, 3) ICs may crack under high pressure. Subsequently, we solved the thermoplastic film’s flow process during the heat compression process using the rigid-plastic FEM (Finite Element method) analysis. We solved the resin temperature and load during the heat pressing process. It was discovered that ICs (0.18mm) could embed into the PETG film (0.2mm) within 13s. Finally, we applied this embedding process with the contactless IC card, which achieved a distance of calls of 100mm.Copyright

Reliability Evaluation of CSP Using New Flip-Chip Bonding Technology: Both-Sided CSP and Single-Sided CSP

Chip-size packaging (CSP) attracts largely attentions due to its lighter, thinner and smaller size. In this study, the deformations and the stresses in the CSP fabricated by non-conductive film stud-bump direct interconnection (NSD) were analyzed. The reliability evaluation of single-sided CSP and both-sided CSP were investigated for heat cycles. The material parameters, i.e. stresses, strains and deformations, for achieving a high reliability of CSP were investigated using a finite element method and experiment. The dependency of the life in single-sided CSP and both-sided CSP on the thicknesses of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively.Copyright