Kazuya Ohuchi

A novel circuit technology with surrounding gate transistors (SGT's) for ultra high density DRAM's

This paper describes a novel circuit technology with Surrounding Gate Transistors (SGTs) For ultra high density DRAMs. In order to reduce the chip size drastically, an SGT is employed to all the transistors within a chip. SGTs connected in series and a common source SGT have been newly developed for the core circuit, such as a sense amplifier designed by a tight design rule. Furthermore, to reduce the inherent cell array noise caused by a relaxed open bit line (BL) architecture, a noise killer circuit placed in the word line (WL) shunt region and a twisted BL architecture within the sense amplifier region combined with a novel separation sensing scheme have been newly introduced. Using the novel circuit technology, a 32.9% smaller chip size can be successfully achieved for a 64-Mb DRAM and 34.4% for a 1-Gb DRAM compared with a DRAM composed of the planar transistor without sacrificing the access time, power dissipation, and V/sub cc/ margin. Furthermore,the effectiveness of this technology is verified by using the circuit simulation of the internal main nodes such as WL and BL. >

A 0.5 V 200 MHz 1-stage 32 b ALU using a body bias controlled SOI pass-gate logic

SOI CMOS with gate-body connection (DTMOS) and body bias controlled SOI pass-gate logic (BCSOI pass-gate) take advantage of individually isolated SOI device active area and reduce threshold voltage by controlling each device body bias. Hence, they enjoy higher speed than circuits based on fixed low threshold voltage. The direct body bias control used in previous work suffers from leakage current at supply voltage higher than 0.8V due to drain-body junction leakage. A practical circuit technology that offers the highest speed, lowest operation voltage and stable operation under wide supply voltage demonstrates performance with an ALU macro using this technology.

A compact on-chip ECC for low cost flash memories

A compact on-chip Error Correcting Code/Circuit (ECC) for low cost Flash memories has been developed to minimize the chip size increase. The proposed on-chip ECC implemented on a 64 M NAND Flash memory has suppressed the chip size penalty to 1.9%. Moreover, the cumulative sector error rate can be improved by 4 orders after 10/sup 6/ write/erase cycles.

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of achieving high performance with gate length scaling. The nitrogen profile in the gate oxynitride was optimized to reduce gate current and to prevent boron penetration in the pFET. The thermal budget in MOL & BEOL processes was reduced to realize shallower junction depth in the S/D extension region and to suppress gate poly-Si depletion. Finally, current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/ = 0.85 V (I/sub off/ = 100 nA//spl mu/m) were achieved, which are the best values in 35 nm gate length CMOS reported to date.

High-resolution characterization of ultrashallow junctions by measuring in vacuum with scanning spreading resistance microscopy

The spatial resolution of scanning spreading resistance microscopy has been limited by using conventional probes when measuring in air. Sufficient electric contact of a probe-sample has been difficult to obtain in air due to the existence of moisture/contamination. Two-dimensional carrier profiling of nanoscale silicon devices is performed in a vacuum with conventional probes, and a high spatial resolution is obtained. Ultrashallow junctions down to 10nm are measured accurately with high reproducibility. Experimental results show that a good electric contact between probe and sample is important for obtaining high spatial resolution.

0.5 V SOI CMOS pass-gate logic

Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.

A new static memory cell based on the reverse base current effect of bipolar transistors

A SRAM cell that consists of a bipolar transistor and an MOS transistor is proposed. The cells principle of operation is based on the reverse base current (RBC) of a bipolar transistor. It has been fabricated by conventional BiCMOS technology, using double-poly Si. A cell size of 8.58 mu m/sup 2/ is realized in a 1.0- mu m ground rule. The mechanism and characteristics of this cell are discussed. >

Impact of BOX scaling on 30 nm gate length FD SOI MOSFET

This paper presents the first demonstration of ultra-thin BOX FD SOI devices with nominal gate length of 30 nm. The characteristics of FD SOI MOSFETs are investigated in detail as T/sub BOX/ is varied from 5 nm to 145 nm. In addition, optimum design regions of T/sub BOX/ for achieving performance requirements are demonstrated.

Junction Leakage Generation by NiSi Thermal Instability Characterized Using Damage-Free n+/p Silicon Diodes

Using n+/p junctions formed by solid phase diffusion, a clear correlation between junction leakage and NiSi thermal instability was readily established. After forming an NiSi layer on damage-free junctions, various post-annealing processes at around the silicidation temperature were applied. A consistent and systematic rise of the leakage level was observed with the increase of the annealing time and the temperature. The migration of the released Ni atoms away from the NiSi layer, the subsequent clustering of the migrant Ni atoms, and the eventual formation of generation-recombination centers deep inside the Si substrate were identified as the basic components of the principal leakage mechanism. Detailed analysis of the thermally stimulated ingressive movement of the leakage-depth profiles revealed a substantial Ni burst at an early stage of annealing. This anomalous Ni burst imposes severe restrictions on junction shallowing for NiSi technology and sets a strict upper limit on the allowable process temperature for effective leakage suppression.

A hp22 nm node low operating power (LOP) technology with sub-10 nm gate length planar bulk CMOS devices

High performance 10 nm gate length CMOSFETs for hp22 nm node LOP is demonstrated for the first time. Key process, such as elevated source/drain extension combined with flash lamp annealing, fully silicided metal gate, novel SiON, and optimization method under high V/sub dd/ condition which taking care of SRAM performance is described. Record high transconductance of 1706 mS/mm and over 400 GHz f/sub i/ is achieved for nMOSFET. Bulk planar MOSFET structure can extend down to hp22 nm node.