Kazuyuki Inokuchi

Modulation of Drain Current by Holes Generated by Impact Ionization in GaAs MESFET

A hole current generated by impact ionization in the channel at high drain voltages is measured using a GaAs MESFET with a conductive buried p layer (CBP-MESFET). The hole injection into the p layer beneath the channel is found to be the origin of the kink effect. A sidegating effect in the CBP-MESFET is also studied. A suppression of the sidegating effect by the negatively biased p layer is shown. An anomolous behavior in the sidegating effect at high drain voltages is observed; it may be related to the holes generated by impact ionization.

Effect of bias sputtering on W and W-Al Schottky contact formation and its application to GaAs MESFETs

The effect of DC bias on the sputter-deposition of W and W-Al on GaAs substrates was investigated. By applying a negative bias to the substrate, the concentration of impurities in the metals and at the interface, such as oxygen, was reduced, and the characteristics of the Schottky contact were improved with respect to the barrier height, the n-value and the uniformity. These results are explained by the reverse sputtering effect for the substrate. This technique was applied to the gate formation of GaAs MESFETs, and the uniformity of the threshold voltage distribution within a 2-inch wafer was much improved.

Asymmetric Implantation Self-alignment Technique for GaAs MESFETs

A novel self-alignment technique, the asymmetric implantation self-alignment technique (ASIST), has been developed for GaAs MESFETs. This technique is based on the selective self-alignment ion implantation which provides an asymmetric n+ profile for the source and drain regions. By ASIST, the GaAs MESFET has been fabricated with the heavily doped source and the lightly doped drain and it is demonstrated for the first time that this structure is quite effective in suppressing the short-channel effect without increasing the source resistance. In this letter, the process and device characteristics of the ASIST-FET are described.

Sub-Quarter-Micron Gate Fabrication Process Using Phase-Shifting Mask for Microwave GaAs Devices

A phase-shifting mask technique using an i-line stepper was applied to the gate formation process of AlGaAs/GaAs high electron mobility transistors (HEMTs). To obtain a fine gate pattern of less than a quarter micron, the phase-shifter edge-line mask, which has the highest resolution and wide focus margin for an isolated pattern, was used and the double exposure process was developed to form a real gate pattern. The controllable gate length was in the range of 0.50-0.15 µm. By using this technique, 0.18 µm-gate HEMTs with good and uniform microwave performances in a 3-inch wafer were obtained. This technique has great advantages for applications to microwave GaAs devices and ultrahigh-speed GaAs LSIs.

A study of GaAs digital ICs on Si substrates

The speed characteristics and the sidegating effect of GaAs metal semiconductor field effect transistors (MESFETs) on Si substrates were studied. The propagation delay of a direct-coupled FET logic (DCFL) inverter with 0.3-μm-gate MESFETs was 19.9 ps/gate, which was about 19.9 ps/gate larger than that for the inverter on undoped liquid-encapsulated Czochralski (LEC) semi-insulating GaAs substrates. As for the sidegating effect, devices on the GaAs on Si (GaAs/Si) substrates showed a smaller decrease in drain current than those on GaAs substrates as side-gate voltage increased