Kazuyuki Mitsukura

3D IC assembly using thermal compression bonding and wafer-level underfill — Strategies for quality improvement and throughput enhancement

This paper examines the key aspects for quality improvement and throughput enhancement of thermal compression bonding (TCB) process using dry film laminated wafer-level underfill (WLUF) material. The WLUF material must have good compatibility with pre-assembly and assembly process steps. And all the process steps after and including WLUF lamination have to be co-optimized to ensure the integrity of the WLUF material, consequently leading to higher stacking yield. Good bump joining and underfill filling quality is achieved by optimization different stages of the TCB profiles. A new method enabled by WULF, termed vertical collective bonding (VCB), is applied to multi-layer 3D stacking, producing good bonding quality and significant process time saving. Multi-layer 3D stacks made by the VCB process show good thermomechanical reliability in high temperature storage and thermal cycling tests.

Material technology for 2.5D/3D package

Packaging material is one of the key components for through-silicon via (TSV) 2.5D/3D package giving a strong impact on the higher density integration and its reliability. We have developed and evaluated our packaging materials by collaborating with 3D system integration program in Interuniversity microelectronics center (IMEC). In this paper, we report the assembly and reliability results on film type underfill, photosensitive dielectric for redistribution layer as well as stress buffer, and molding compound. In the case of using our film type underfill, five-chip stacked package with TSV and 20 μm pitch bumps was demonstrated with excellent electrical yield. Also photosensitive dielectric realizes redistribution layers with 3 μm resolution. Finally we integrated our film type underfill, dielectric and molding compound in the stacked package, passing reliability tests such as thermal cycling and pressure cooker test.

Photosensitive insulation coating for a copper redistribution layer process

Redistribution on a through-silicon via (TSV) with a copper interconnection and dielectric layer is one of the key components for a silicon-based interposer. In this paper, we report lithographic and mechanical performance for a positive-tone photosensitive insulation coating, CA6001B. Minimum resolution for CA6001B is 3 μm determined by electrical measurement with a test wafer having a copper redistribution and the patterned insulation layers. The CA6001B is one of the promising dielectric coatings for interposers possessing TSV and redistribution layer (RDL) structures.