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Dive into the research topics where Kazuyuki Wada is active.

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Featured researches published by Kazuyuki Wada.


IEEE Journal of Solid-state Circuits | 2009

A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-

Ippei Akita; Kazuyuki Wada; Yoshiaki Tadokoro

This paper presents a 100-kHz fifth-order Chebychev low-pass filter (LPF) using the proposed dynamic biasing (DB) technique which enables wide dynamic range under a low-supply voltage. The change of state variables in the internal nodes of the filter can be corrected by using a novel simplified scheme, avoiding the output transient owing to dynamic biasing. The filter, including an automatic frequency tuning system based on the voltage-controlled-filter (VCF) architecture and voltage reference circuit, is fabricated in a 0.18-mum standard CMOS technology with a 0.5-V threshold voltage and consumes 443 muW from a power supply of 0.6 V. The output noise and the in-band IIP3 are 575 pArms and 219 muA, respectively. The filter achieves a dynamic range of 89 dB.


international symposium on circuits and systems | 2002

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Kazuyuki Wada; Yoshiaki Tadokoro

A scheme reducing error on source followers due to the body effect is proposed. A node of a source follower which has been connected to a DC voltage source is excited by a control circuit so that an output signal is well compensated. The scheme employs an additional source follower for detecting error of an original source follower. Since the error is algebraically analyzed, a characteristic of a control circuit for tuning the node potential is solved. Based on the scheme a level-shift circuit is given and its effectiveness is confirmed through computer simulations and application to the bias-offset technique.


international symposium on circuits and systems | 2001

m CMOS

Shigetaka Takagi; Nicodimus Retdian Agung; Kazuyuki Wada; Nobuo Fujii

This paper proposes a digital noise reduction technique called active guard band. No need of any external elements enables the overall circuit to be implemented on the same chip with a main system. The proposed basic circuit will provide noise suppression level of -10 dB at frequencies up to 100 MHz with maximum suppression level of -14 dB. Meanwhile, noise suppression level of -15 dB at frequencies up to 100 MHz and maximum suppression level of about 10 dB are achieved using its improved version.


international symposium on circuits and systems | 2003

Design of a body-effect reduced-source follower and its application to linearization technique

Kazuyuki Wada; Yoshiaki Tadokoro

This paper proposes a design of RC polyphase filters with flat gain characteristics in the passband and equi-ripple ones in the stopband. The time constants of cascaded sections are given by an equation in explicit form. Resistances and capacitances for optimum filters are obtained by solving an equation which is a polynomial of only one unknown parameter. Design examples are shown and effectiveness of the design is confirmed from simulation results.


IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2008

Active guard band circuit for substrate noise suppression

Shigetaka Takagi; Retdian A. Nicodimus; Kazuyuki Wada; Takahide Sato; Nobuo Fujii

A multi-path structure is proposed for reduction in effect of digital substrate noise which degrades analog circuit performance. As an example low-pass filters are implemented in a 0.18-μm CMOS process. 11-dBm reduction in digital substrate noise is achieved as compared with a conventional structure.


international symposium on circuits and systems | 2000

RC polyphase filter with flat gain characteristic

Sohrab Emami; Kazuyuki Wada; Shigetaka Tagaki; Nobuo Fujii

A new architecture for class A CMOS current conveyor is proposed. The proposed circuit is free from the body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation using 2 /spl mu/m process parameters also confirms the effectiveness of the proposed circuit.


Analog Integrated Circuits and Signal Processing | 1998

Multi-Path Analog Circuits Robust to Digital Substrate Noise

Kazuyuki Wada; Shigetaka Takagi; Nobuo Fujii

This paper proposes an automatic tuning system to adjust frequency characteristics of integrated continuous-time filters especially at high frequencies. Frequency characteristic deterioration of a filter using integrators with electrically controllable unity-gain frequencies can be easily evaluated and compensated even when they are affected by deviations of element values and parasitic elements. The compensation requires detection of both frequency and excess phase shifts of the integrators. Their two values are electrically detected by two detection systems usually used in the conventional frequency tuning system. The proposed system is stable, simple and easy to be implemented on an integrated circuit. As an example a 4th-order biquad bandpass filter with 10 MHz center frequency, 2 MHz passband width, and 0.5 dB passband ripples is designed using a bipolar process. Simulation results by SPICE show the effectiveness of the proposed system.


IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2007

A novel class A CMOS current conveyor

Hiroto Suzuki; Kazuyuki Wada; Yoshiaki Tadokoro

Band connections employed in active cancellation circuits for effective reduction of digital substrate noise are proposed. An almost-odd-symmetrical noise characteristic is utilized for canceling out noises. Advancing this idea, interlaced connections of four bands are also proposed. Excess cancellation by those bands is more effective for noise reduction in a guard ring than a cancellation by two bands. Use of L-shaped bands on the basis of the interlaced connection suppresses the noise more. Simulation and experimental results show that the proposed band connections reduce the noise.


international symposium on circuits and systems | 2006

Automatic Tuning System for Integrator-Based Continuous-Time Filters

Ippei Akita; Kazuyuki Wada; Yoshiaki Tadokoro

This paper proposes a low-voltage syllabic companding log domain filter without state variable correction circuits, which is needed for externally linear and time-invariant operation of conventional filters. The proposed filter is simplified and has wide input range under low-supply voltage by varying a nodal voltage adaptively. The simulation results show 60-dB input range for over 40-dB signal to noise plus distortion ratio at a power supply of 0.6 V in a 0.18-mum CMOS process.


asia pacific conference on circuits and systems | 2000

Band Connections for Digital Substrate Noise Reduction Using Active Cancellation Circuits

Takahide Sato; Mamoru Nakamura; Shigetaka Takagi; Kazuyuki Wada; Nobuo Fujii

This paper proposes a low-distortion CMOS operational transconductance amplifier (OTA) based on backgate-bias technique especially for an OTA using four MOSFETs operating in the non-saturation region as a voltage controlled current source (VCCS). In the VCCS two input signals are applied to two drain terminals of the four MOSFETs respectively and their gate-to-source voltages are kept constant. Therefore the VCCS is free from mobility reduction. To make backgate-to-source voltages of two MOSFETs in the VCCS equal to DC shift of input signals will reduce output current distortion of the OTA drastically. In addition to these features the proposed OTA is free from body effect even when it is realized by a single well process. Simulation results confirm the theory and the effectiveness of the proposed method.

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Shigetaka Takagi

Tokyo Institute of Technology

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Nobuo Fujii

Tokyo Institute of Technology

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Yoshiaki Tadokoro

Toyohashi University of Technology

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Hiroto Suzuki

Toyohashi University of Technology

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Retdian A. Nicodimus

Tokyo Institute of Technology

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Ippei Akita

Toyohashi University of Technology

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Takahide Sato

Tokyo Institute of Technology

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Nobuo Fujii

Tokyo Institute of Technology

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Shigetaka Takagi

Tokyo Institute of Technology

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