Kedarnath J. Balakrishnan

Improving Linear Test Data Compression

The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping all the test cubes in the output space. Scan inversion is used to invert a subset of the scan cells while reconfiguration modifies the linear decompressor. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed methods improve the compression further. The key property of scan inversion is that it is a linear transformation of the output space and, thus, the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize compression. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for reconfiguring the linear decompressor. The proposed schemes can be utilized in various design flow scenarios and require no or very little hardware overhead. Experiments indicate that significant improvements in compression can be achieved

X-Block: An Efficient LFSR Reseeding-Based Method to Block Unknowns for Temporal Compactors

This paper presents an efficient method to block unknown values for temporal compactors. The control signals for the blocking logic are generated by a linear feedback shift register (LFSR). Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. The size of the control LFSR, which is determined by the number of specified bits in the most specified control pattern, is minimized by propagating only one fault effect for each fault and targeting the faults that are uniquely detected by each test pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Very high compression (over 230X) is achieved for benchmark and industrial circuits by the proposed method. Experimental results show that the sizes of control data for the proposed method are smaller than prior work and the runtime of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low.

Reconfigurable Linear Decompressors Using Symbolic Gaussian Elimination

A methodology for designing a reconfigurable linear decompressor is presented. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for designing the reconfigurable network. The proposed scheme can be implemented in conjunction with any decompressor that has a combinational linear network. Using the given linear decompressor as a starting point, the proposed method improves the compression further. A nice feature of the proposed method is that it can be implemented with very little hardware overhead. Experimental results indicate that significant improvements can be achieved.

Improving encoding efficiency for linear decompressors using scan inversion

The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The idea proposed in This work is to use scan inversion to transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing the encoding efficiency while still keeping all the test cubes in the output space. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed method improves the encoding efficiency further. The key property used by the proposed method is that scan inversion is a linear transformation of the output space and thus the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize encoding efficiency. Experiments indicate that significant improvements in encoding efficiency can be achieved.

Matrix-based test vector decompression using an embedded processor

This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the processors on-chip memory. The processor executes a program which decompresses the data and applies it to the scan chains of each core-under-test. The matrix-based operations that are used to decompress the test vectors can be performed very efficiently by the embedded processor thereby allowing the decompression program to be very fast and provide high throughput of the test data to minimize test time. Experimental results demonstrate that the proposed approach provides greater compression than previous methods.

Compressing Functional Tests for Microprocessors

In the past, test data volume reduction techniques have concentrated heavily on scan test data content. However, functional vectors continue to be utilized because they target unique defects and failure modes. Hence, functional vector compression can help alleviate the cost of functional test. Scan vector compression techniques are generally unsuitable in the functional domain and techniques specially tailored for functional test compression are required. Additionally, it may be possible to perform compression and decompression using software techniques without incurring the overhead of dedicated hardware. This paper proposes a set of software techniques targeted towards functional test compression.

XWRC: externally-loaded weighted random pattern testing for input test data compression

This paper presents an input test data compression scheme that combines the advantages of weighted pseudorandom testing techniques and LFSR reseeding. The scheme requires low area overhead and the compression achieved is not limited by the LFSR reseeding bounds. The test data storage requirements of both the static and dynamic versions of the proposed scheme are lower than previously published results. The total numbers of test patterns that need to be applied are much lower than that for any weighted pseudorandom testing or hybrid BIST scheme. Further, the method provides an easy way to trade off between test application time and test data compression. The static version of the scheme can be easily implemented without any modification to the current test generation flow while the dynamic version can be used if the ATPG can be modified. Experimental results on a large industry design show that over 100times compression is achievable by the proposed scheme

PIDISC: pattern independent design independent seed compression technique

A novel scheme for compressing the seeds of a linear feedback shifter register (LFSR) is presented. Instead of storing the seeds of the LFSR in the tester, the scheme compresses the seeds and stores them in the tester. The compression scheme can be used with any variation of static LFSR reseeding. An important feature of the proposed scheme is that the decompressor is test pattern and design independent and can be implemented with very little area overhead. Experimental results show that seed compression can improve overall compression by a factor of 7/spl times/ for large industrial circuits.

RTL Test Point Insertion to Reduce Delay Test Volume

In this paper, a novel test point insertion methodology is presented for RTL designs that aim to reduce the data volume of scan-based transition delay tests. Test points are identified based on functional information of RTL primitives using a satisfiability based algorithm. A subset of scan flip-flops is identified for conversion to enhanced-scan, i.e., the values are stored in two flip-flops thereby removing the circuit dependency of the second pattern in broadside transition tests. Using the proposed methodology, the number of specified bits required to test transition faults is reduced thus improving test set compaction. The advantage of test point insertion at RTL is that the extra delay due to multiplexers can be absorbed during logic synthesis. Experimental results show that the proposed methodology can reduce transition test data volume by more than 30% with 1% area overhead and without violating timing constraints.

Matrix-based software test data decompression for systems-on-a-chip

This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test vectors for each core are compressed using matrix-based operations that significantly reduce the amount of test data that needs to be stored on the tester. The compressed data is transferred from the tester to the processors on-chip memory. The processor executes a program which decompresses the data and applies it to the scan chains of each core-under-test. The matrix-based operations that are used to decompress the test vectors can be performed very efficiently by the embedded processor thereby allowing the decompression program to be very fast and provide high throughput of the test data to minimize test time. Experimental results demonstrate that the proposed approach provides greater compression than previous methods.