Keeho Kim

Simulation based post OPC verification to enhance process window, critical failure analysis, and yield

Optical Proximity Correction (OPC) often reaches its limitation, especially low-k imaging. It results in yield drop by bridging, pinching, and other process window sensitive issues. It happens more when the original layout contains OPC-unfriendly patterns. With OPC-unfriendly layout, OPC model generates totally unexpected results such as narrow space, small jog, small serif and etc. Those unexpected OPC results induce bridged patterns as well as narrow process margin. And they will give direct yield loss of device. Thus, it is critical to implement the flow for Litho Friendly Design (LFD) and nevertheless simulation-based OPC verification. In this study, a new approach of OPC has been tested, which contains the simulation based analysis of OPC failure and in turn out reconstruct OPC features in a way to fix not only bridging and pinching but also to improve process window. This proves to reduce mask respin by 50% or more. It also has been tried to be a complementary checking in addition to conventional CD monitor in pilot production.

The study for increasing efficiency of OPC verification by reducing false errors from bending pattern by using different size of CD error non-checking area with various corner lengths

In recent years, model based verification for optical proximity effect correction (OPC) has become one of the most important items in semiconductor industry. Major EDA companies have released various softwares for OPC verification. They have continuously developed and introduced new methods to achieve more accurate results of OPC verification. The way to detect only real errors by excluding false errors is the most important thing for accurate and fast verification process, because more time and human resource are needed to inspect the result of verification as increasing false errors. A major source of false errors is bending patterns. The number of those from bending patterns is over thousands and they are inevitable. The most verification tools have the scheme for excluding those by using CD error non-checking or filtering area. Real errors around bending pattern will not be able to detect with too big size of area, while too many false error will be reported with too small size of area. Since currently most verification tools had only a fixed area size for filtering, it has been impossible to achieve most accurate and efficient verification results. Through the optimization of area size with different corner length, we could get more accurate and efficient results and decrease the time for review to find real errors. In this paper, the suggestion in order to increase efficiency of OPC verification process by using different size of CD error non-checking area with various corner lengths is presented.

Optimization of lithography process to improve image deformation of contact hole sub-90 nm technology node

In resolution limited lithography process, the image deformation is getting severer. This is very important area where we need to fully understand and improved since the image deformation is directly giving poor CD control effect. Especially, contact hole image will be more sensitive since it has lower k1 factor that line and spaced pattern. This image deformation of contact hole can give some severe electrical fail due to not opened contact. In our case, we observed some critical failure mode of diagonal induced by abnormal contact hole shape of rough edge. In this paper, we investigate how deformed contact hole image impacted on degradation of device performance in electrical properties and yield and how we can improve it. To quantitatively analyze image deformation of contact hole, we recommend new measurement method first. This new measurement gives exact image deformation amount at different experimental conditions. Finally, we will show how experimental conditions such as soft bake temperature, post expose bake temperature, hardening bake temperature, illumination condition and mask bias change image deformation of contact hole.

Enhanced hole shape of flash devices in ArF lithography by eliptical mask bias technique

As the resolution requirement downing 90 nm beyond, hole pattern is one of the most challenging features to print in the semiconductor manufacturing process. Especially, when hole patterns have dense array of holes as they are consisted of several columns with single row, there can be serious distorted form from desired patterns such as oval hole shape and bridge between holes. It is due to nature of diffraction which generates interaction of diffracted light from near holes. Overlap margin reduction by hole shape change as oval shape is very harmful in sub-90nm photolithography process which has very narrow overlay margin. To increase overlap margin, it is necessary to solve these phenomenon. Optical Proximity Correction (OPC) has been used for overcoming oval hole shape. Through the result of OPC modeling and simulation, we could get optimized mask bias of hole. Sometimes, good experimental data will be help for this modeling and OPC process. From these OPC simulation and experimental data, most compatible rule based OPC process could be developed. In this paper, we suggest the method of improving oval hole shape by using OPC simulation and making rule base OPC process from experimental data.

Efficient approach to improving pattern fidelity with multi-OPC model and recipe

It is becoming difficult to achieve stable device functionality and yield due to the continuous reduction of layout dimensions. Lithographers must guarantee pattern fidelity throughout the entire range of nominal process variation and diverse layout. Even though we use general OPC method using single model and recipe, we usually expect to obtain good OPC results and ensure the process margin between different devices in the sub-100nm technology node. OPC Model usually predicts the distortion or behavior of layout through the simulation in the range of measured data. If the layout is out of range from the measured data, or CD difference occurred from the topology issue, we can not improve the OPC accuracy with a single OPC model. In addition, as the design rule has decreased, it is extremely hard to obtain the efficient OPC result only with a single OPC recipe. We can not extract the optimized single OPC recipe which can cover all the various device and layout. Therefore, we can improve the OPC accuracy and reduce the turn around time related to the OPC operation and mask manufacturing in sub-100nm technology node by applying the optimized multi OPC recipes to the device which contains the various patterns like SoC.

Fundamental study on the error factor for sub 90nm OPC modeling

In low-k1 imaging lithography process it is difficult to make the accurate OPC model not only because of factors caused by unstable process such as large CD (Critical Dimension) variation, large MEEF (Mask Error Enhancement Factor) and very poor process window but also because of potential error factors induced during OPC model fitting. In order to minimize those issues it is important to reduce the errors during OPC modeling. In this study, we have investigated the most influencing error factors in OPC modeling. At first, through comparing influence of optical parameters and illumination systems on OPC runtime and model accuracy, we observe main error factor. Secondly, in the case of resist modeling, OPC runtime and model accuracy were also analyzed by various model forms.

A study for effect of rounded contact hole pattern by laser mask writing machine onto wafer process margin

The higher productivity of the DUV laser mask lithography system compared to the 50-KeV e-beam system offers the benefit of mask cost down at low k1 lithographic process. But the major disadvantage of the laser mask writing system is rounding effect of contact hole and line end. In this paper, we study wafer process margin effect of corner rounded contact hole and present mask CD specification of corner rounded contact hole written by DUV laser lithography system compared to 50KeV writing tool. The contact hole rounding changes contact hole area at the same mask CD and also change MEEF(Mask Error Enhancement Factor) even though the contact hole area is compensated by adjusting mask bias. If one change EBM3500 mask writer machine to Alta4300 mask writer machine for 160nm contact hole using KrF and 6% HT-PSM, one has to change mask bias, 3.2nm, to meet same wafer process condition.. The MEEF of ALTA4300 mask is 1.6% higher than that of EBM3500 mask at same effective target mask CD. And the mask CD specification written by ALTA4300 has to be set more tightly about 1.3 ~ 1.5% to meet same wafer process margin with EBM3500 mask.

Methodology to set up mask CD specification including MEEF and process sensitivity of mask CD error

The advanced lithography needs to be tightly controlled in various areas of lithography. The mask CD specification is one of new areas required much tighter control. Typically, mask CD error can be sorted as two different categories. One is Mean-to-target (MTT) and another is CD uniformity (CDU). The MTT is the difference between the target value and the average value of the measured CD on the mask. CDU means CD uniformity across mask. Those two potential errors can be magnified on the wafer level due to the MEEF. To overcome the MTT, we can adjust expose dose to compensate mask CD error so that we achieve targeted CD on the wafer level. However, the changing expose dose also induces process window change due to the MEEF. It means that we have narrower process window even if we get the targeted CD on the wafer level. On the other hand, CDU can give two different effects on the wafer level. One is narrower process window due to magnified ACLV (Across Chip Line-width Variation) due to the MEEF. Another effect of CDU is the poor OPC accuracy caused by different MEEF as function of pitch. For example, we assume that CD difference of dense line and isolated line is 10 nm on the mask. However, on the wafer, this 10 nm can be magnified as 20 nm by MEEF difference between two structures. Therefore, we think that the mask specification needs to take account those effects. In this paper, we will show technical data to prove how MTT and CDU impact on process window and OPC accuracy. And we will show how we have to make mask specification to overcome those effects.

Mask process variation induced OPC accuracy in sub-90nm technology node

Since an OPC engine makes model to fit wafer printed CD of OPC test mask to simulation CD of test pattern layout, the target CD of OPCed mask is not design CD but the CD of OPC test mask. So, the CD difference between OPC test mask and OPCed mask is one of the most important error source of OPC. We experimentally obtained OPC CD error of several patterns such as iso line, iso space, dense line, line end, effected by the mask MTT (mean to target) difference of the two masks on of 90nm logic pattern with an ArF attenuated mask having designed different MTT. The error is compared to simulated data that is calculated with MEEF (mask error enhancement factor) and EL (exposure latitude) data of these patterns. The good agreement of the experimental and calculated OPC error effected mask MTT error can make OPC error are predicted by mask CD error. Using by these calculation, we made mask CD window to meet OPC spec for 90nm ArF process.

The effect of sub-layer condition on the OPC model

OPC(Optical Proximity Correction) has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD (Critical Dimension) control as design rule shrinks. Current model based OPC is a combination of optical and process model to predict lithography process. At this time, the accurate OPC model can be made by accurate empirical measurement data. Therefore empirical measurement data affects OPC model directly. In the case of gate layer, it affects to device performance significantly and CD spec is controlled tightly. Because gate layer is hanging on between active area and sti area, the gate CD is affected by different sub layer stack and step height. This paper will analyze that the effect of sub layer on the OPC model and show difference EPE value results at the patterns such as iso line, iso space,pitch, line end and T_junction between poly and gate model using constant threshold model.