Keichi Takahashi

Performance evaluation of SDN-enhanced MPI allreduce on a cluster system with fat-tree interconnect

Nowadays, supercomputers play an essential role in high-performance computing. In general, modern supercomuputers are built as a cluster system, which is a system of multiple computers interconnected on a network. In coding a parallel program on such a cluster system, MPI (Message Passing Interface) is utilized. In this paper, we aim to reduce the execution time of MPI Allreduce, a frequently used MPI collective communication in many simulation codes. To this end, we have integrated network programmability by Software Defined Networking into MPI Allreduce so that it effectively uses the bandwidth of the interconnect of the cluster system. An experiment conducted on a cluster system with fat-tree interconnect indicates that our proposed MPI Allreduce is superior to MPI Allreduce in OpenMPI implementations.

Concept and Design of SDN-Enhanced MPI Framework

In general, modern high-performance computing systems are built as cluster systems. We have been investigating the feasibility of optimizing MPI communications by integrating the dynamic network control realized by SDN. In this paper, we present a concept of a generic SDN enhanced MPI framework, an application-aware network control mechanism specifically for MPI applications.

An Empirical Study of SDN-accelerated HPC Infrastructure for Scientific Research

High performance computing is required for Big Science application because the proliferation and huge amount of scientific data that needs to be analyzed is a serious problem. Traditionally, network resources were generally assumed as a static resource users cannot control on demand. By integrating network programmability to every stage of a scientific workflow, this study explores a next-generation high performance computing infrastructure where both computational and network resources are flexibly sliced and efficiently leveraged based on the resource requirements of the scientific applications. Technically, Software Defined Networking has been adopted as a key technology for this purpose. In this paper the concept and goals of a next-generation high performance computing infrastructure is introduced and the current status of our research is discussed.

Design and implementation of control sequence generator for SDN-enhanced MPI

MPI (Message Passing Interface) offers a suite of APIs for inter-process communication among parallel processes. We have approached to the acceleration of MPI collective communication such as MPI_Bcast and MPI_Allreduce, taking advantage of network programmability brought by Software Defined Networking (SDN). The basic idea is to allow a SDN controller to dynamically control the packet flows generated by MPI collective communication based on the communication pattern and the underlying network conditions. Although our research have succeeded to accelerate an MPI collective communication in terms of execution time, the switching of network control functionality for MPI collective communication along MPI program execution have not been considered yet. This paper presents a mechanism that provides the control sequence for SDN controller to control packet flows based on the communication plan for the entire MPI application. The control sequence encloses a chronologically ordered list of the MPI collectives operated in the MPI application and the process-related information of each in the list. To verify if the SDN-enhanced MPI collectives can be used in combination with the proposed mechanism, the envisioned environment was prototyped. As a result, SDN-enhanced MPI collectives were able to be used in combination.

MPI_Reduce algorithm for OpenFlow-enabled network

The MPI reduction operation such as MPI_Reduce and MPI_Allreduce are frequently used and time-consuming operations. The performance enhancement of these operations can substantially speed up large-scale parallel applications. In this paper, a greedy based MPI_Reduce algorithm called Greedy Shortest Binomial Tree (GSBT) is proposed. This proposed algorithm leverages SDN technology and OpenFlow network to speed up MPI reduction operations. This is accomplished using network topology information from the OpenFlow controller to reduce overall hops in message transmission. The implementation of the proposed algorithm by modifying MPI library and OpenFlow controller is presented. The proposed GSBT algorithm has been evaluated in a real test-bed to compare with the traditional approaches used in both MPICH and Open MPI. The result shows that GSBT algorithm is faster than standard algorithms 30.48-66.35% for Open MPI and faster 50.77-82.89% for MPICH when message size between 2 KB - 24 KB.

Toward Flexible Supercomputing and Visualization System

The Cybermedia Center is a research institute in Osaka University, which is in charge of administrating high-performance computing systems and high-speed networks for research and education. Especially in the era where the proliferation of scientific data to analyze is accelerating, limited and finite computational and network resources are to be efficiently and flexibly leveraged and shared among scientists. Also, computing requirements for supercomputing and visualization such as memory bandwidth, computational performance and scalability vary widely depending on the applications. Therefore, designing a supercomputing and visualization system which fits to all applications in advance is becoming more difficult. From such a perspective, this paper presents our center’s research activities to realize the concept of flexible supercomputing and visualization as well as its progress report by introducing a new attracting notion of SDN (Software Defined Networking) and its northbound APIs.

PFAnalyzer: A Toolset for Analyzing Application-Aware Dynamic Interconnects

Recent rapid scale out of high performance computing systems has rapidly and continuously increased the scale and complexity of the interconnects. As a result, current static and over-provisioned interconnects are becoming cost-ineffective. Against this background, we have been working on the integration of network programmability into the interconnect control, based on the idea that dynamically controlling the packet flow in the interconnect according to the communication pattern of applications can increase the utilization of interconnects and improve application performance. Interconnect simulators come in handy especially when investigating the performance characteristics of interconnects with different topologies and parameters. However, little effort has been put towards the simulation of packet flow in dynamically controlled interconnects, while simulators for static interconnects have been extensively researched and developed. To facilitate analysis on the performance characteristics of dynamic interconnects, we have developed PFAnalyzer. PFAnalyzer is a toolset composed of PFSim, an interconnect simulator specialized for dynamic interconnects, and PFProf, a profiler. PFSim allows interconnect researchers and designers to investigate congestion in the interconnect for an arbitrary cluster configuration and a set of communication patterns collected by PFProf. PFAnalyzer is used to demonstrate how dynamically controlling the interconnects can reduce congestion and potentially improve the performance of applications.

Dynamic Reconfiguration of Computer Platforms at the Hardware Device Level for High Performance Computing Infrastructure as a Service

Users’ needs and requirements for high performance computing (HPC) has become increasingly diversified. As user needs become increasingly diverse, it becomes increasingly difficult to own high-performance computing platforms themselves and the HPC platform provider are required to provide computing platforms to execute diverse applications. In this paper, we propose a computer architecture for providing HPC infrastructure dynamically and promptly as a cloud computing service in response to users’ request for computing platforms. In order to gain flexibility to accommodate various HPC jobs with application specific computing platforms, the proposed system reconfigures a software and hardware platform by utilizing the synergy of Open Grid Scheduler/Grid Engine and OpenStack. The experimental system developed in this research shows the high flexibility of hardware platform reconfiguration and the high performance of Spark’s benchmark application. In addition, our simulation evaluation shows that dynamic reconfigurable hardware cluster system can improve hardware resource utility rate, and also eliminating the worst case of resource congestion in the real-world operational record of our university’s computer center during the first half of 2016.