Keigo Otsuka

Water-assisted self-sustained burning of metallic single-walled carbon nanotubes for scalable transistor fabrication

Although aligned arrays of semiconducting single-walled carbon nanotubes (s-SWNTs) are promising for use in next-generation electronics owing to their ultrathin bodies and ideal electrical properties, even a small portion of metallic (m-) counterparts causes excessive leakage in field-effect transistors (FETs). To fully exploit the benefits of s-SWNTs for use in large-scale systems, it is necessary to completely eliminate m-SWNTs from as-grown SWNT arrays and thereby obtain purely semiconducting large-area arrays, wherein numerous FETs can be flexibly built. In this study, we performed electrical burning of m-SWNTs assisted by water vapor and polymer coating to eliminate m-SWNTs over a long length for the scalable fabrication of transistors from the remaining s-SWNT arrays. During the electrical-breakdown process, the combination of water vapor and the polymer coating significantly enhanced the burning of the SWNTs, resulting in a self-sustained reaction along the nanotube axis. We found that m-SWNT segments partially remaining on the anode side resulted from one-way burning from the initial breakdown position, where Joule-heating-induced oxidation first occurred. The s-SWNT-enriched arrays obtained were used to fabricate multiple FETs with a high on-off current ratio. The results indicate the advantages of this approach over conventional electrical breakdown for the large-scale purification of s-SWNTs.

Field emission and anode etching during formation of length-controlled nanogaps in electrical breakdown of horizontally aligned single-walled carbon nanotubes

We observe field emission between nanogaps and voltage-driven gap extension of single-walled carbon nanotubes (SWNTs) on substrates during the electrical breakdown process. Experimental results show that the gap size is dependent on the applied voltage and humidity, which indicates high controllability of the gap size by appropriate adjustment of these parameters in accordance with the application. We propose a mechanism for the gap formation during electrical breakdown as follows. After small gaps are formed by Joule heating-induced oxidation, SWNTs on the anode side are electrochemically etched due to physically-adsorbed water from the air and the enhanced electric field at the SWNT tips. Field emission is measured in a vacuum as a possible mechanism for charge transfer at SWNT gaps. The relationship between the field enhancement factor and geometric features of SWNTs explains both the voltage dependence of the extended gap size and the field emission properties of the SWNT gaps. In addition, the similar field-induced etching can cause damage to adjacent SWNTs, which possibly deteriorates the selectivity for cutting metallic pathways in the presence of water vapor.

On-Chip Sorting of Long Semiconducting Carbon Nanotubes for Multiple Transistors along an Identical Array

Ballistic transport and sub-10 nm channel lengths have been achieved in transistors containing one single-walled carbon nanotube (SWNT). To fill the gap between single-tube transistors and high-performance logic circuits for the replacement of silicon, large-area, high-density, and purely semiconducting (s-) SWNT arrays are highly desired. Here we demonstrate the fabrication of multiple transistors along a purely semiconducting SWNT array via an on-chip purification method. Water- and polymer-assisted burning from site-controlled nanogaps is developed for the reliable full-length removal of metallic SWNTs with the damage to s-SWNTs minimized even in high-density arrays. All the transistors with various channel lengths show large on-state current and excellent switching behavior in the off-state. Since our method potentially provides pure s-SWNT arrays over a large area with negligible damage, numerous transistors with arbitrary dimensions could be fabricated using a conventional semiconductor process, leading to SWNT-based logic, high-speed communication, and other next-generation electronic devices.

Digital Isotope Coding to Trace the Growth Process of Individual Single-Walled Carbon Nanotubes

Single-walled carbon nanotubes (SWCNTs) are attracting increasing attention as an ideal material for high-performance electronics through the preparation of arrays of purely semiconducting SWCNTs. Despite significant progress in the controlled synthesis of SWCNTs, their growth mechanism remains unclear due to difficulties in analyzing the time-resolved growth of individual SWCNTs under practical growth conditions. Here we present a method for tracing the diverse growth profiles of individual SWCNTs by embedding digitally coded isotope labels. Raman mapping showed that, after various incubation times, SWCNTs elongated monotonically until their abrupt termination. Ex situ analysis offered an opportunity to capture rare chirality changes along the SWCNTs, which resulted in sudden acceleration/deceleration of the growth rate. Dependence on growth parameters, such as temperature and carbon concentration, was also traced along individual SWCNTs, which could provide clues to chirality control. Systematic growth studies with a variety of catalysts and conditions, which combine the presented method with other characterization techniques, will lead to further understanding and control of chirality, length, and density of SWCNTs.