Keisuke Kawamura

Analysis of Buried-Oxide Dielectric Breakdown Mechanism in Low-Dose Separation by Implanted Oxygen (SIMOX) Substrates Fabricated by Internal Thermal Oxidation (ITOX) Process

Buried-oxide (BOX) dielectric breakdown behavior of low-dose separation by implanted oxygen (SIMOX) substrates fabricated by the internal thermal oxidation (ITOX) process was analyzed. From the time-zero dielectric breakdown (TZDB) characterization of the metal-oxide-semiconductor (MOS) capacitors using BOX as a dielectric, of various areas, BOX breakdown was found to be dominated by the electrically weak spots (EWSs) distributed randomly in the BOX layer. The densities of EWSs show good correlation with those of Si islands in the BOX for several samples, indicating that the Si islands are the main cause of BOX breakdown. A model for extracting the EWS density as a function of breakdown field is proposed, the appropriateness of which is verified by its application to the experimental results. Using the proposed model, the dependence of Si island density and their thickness distribution on oxygen ion dose and ITOX layer thickness was investigated, indicating that both dose reduction and ITOX enhancement can effectively reduce the Si island density. By combining the dose reduction and ITOX enhancement, BOX breakdown characteristics, almost comparable to that of the thermally grown oxide were attained, even for a relatively large capacitor area of 7.85×10-3 cm2, revealing the high performance of ITOX-SIMOX technology.

MOVPE growth of GaN on Si substrate with 3C-SiC buffer layer

We investigated the effect of the thickness of a 3C-SiC buffer layer on the growth of GaN on a Si substrate. GaN samples with thicknesses of 2.0 and 4.5 µm were grown by metal organic vapor phase epitaxy. Islands were observed at the initial growth of the GaN samples, and they became larger and then coalesced with each other with increasing growth time. The crystalline quality of the GaN samples was affected by the thickness of the 3C-SiC buffer layer and was improved by increasing their thickness. This indicates that the crystalline quality trend for thick GaN growth is different from that for initial GaN growth. Moreover, the GaN sample with a 100-nm-thick SiC buffer layer had a low initial curvature, and the crystalline qualities on GaN(0004) and planes were 389 and 460 arcsec for 4.5-µm-thick GaN growth, respectively.

Realization of Maskless Epitaxial Lateral Overgrowth of GaN on 3C-SiC/Si Substrates

By virtue of the poor nucleation of GaN on 3C-SiC, a maskless epitaxial lateral overgrowth (ELO) of GaN was realized on 3C-SiC/Si substrates to improve crystalline quality. The mechanism of the maskless ELO process was investigated by observing surface morphologies at different growth steps. Scanning electron microscopy (SEM) and X-ray diffraction (XRD) confirmed that the grain size of GaN crystallites was increased in the three-dimensional ELO. As a result, the stress in the GaN epilayer decreased with the smaller number of grain boundaries in the coalescence process. The luminescent property was also improved with a decrease in defect density.

Study of High-Quality and Crack-Free GaN Growth on 3C-SiC/Separation by Implanted Oxygen (111)

We investigated the growth of GaN on 3C-SiC fabricated by the deposition and carbonization of a separation by implanted oxygen (SIMOX) surface. The dependences of AlN buffer thickness on the crystalline quality and surface morphology of the GaN grown on 3C-SiC/SIMOX (111) by low-pressure metal-organic vapor phase epitaxy (LP-MOVPE) were examined. We studied the stress of GaN by the in situ monitoring of the reflectance and substrate curvature. High-quality GaN with a smooth surface was obtained using an AlN buffer of 10 nm thickness. Moreover, the fabrication of crack-free GaN was achieved using an AlN/GaN superlattice (SL) structure on an AlGaN/AlN buffer.

Gate oxide integrity on ITOX-SIMOX substrates and influence of test device geometry on characterization

The integrity of gate oxides on low-dose separation by implanted oxygen (SIMOX) substrates fabricated by the internal-thermal-oxidation (ITOX) process, so-called ITOX-SIMOX substrates, was evaluated, and the influence of test device geometry on the characterization was investigated. Characterization of time-dependent dielectric breakdown (TDDB) was performed for a gate oxide of 8.6-nm thick using lateral test devices. Experimental results show considerable influence of gate electrode geometry on the gate oxide integrity (GOI) characteristics. This can be explained by a model that includes a lateral parasitic resistance in the superficial Si layer beneath the gate electrode. Based on analysis using this model, a test device with a small gate array was proposed to reduce the influence of lateral parasitic resistance, and the advantage of the device was verified.

Current-Path Observation in Low-Dose SIMOX(Separation by Implanted Oxygen) Buried-SiO2 Layer.

Current paths in the buried- SiO2 layer of low-dose SIMOX (Separation by IMplanted OXygen) wafers are observed directly by micro-beam techniques both in plan and sectional views based on Cu-plated indications. Large-area current paths display particle traces on the surface-Si layer immediately above the current path. Higher annealing temperatures (≥1330° C) decrease micro-roughness along the buried- SiO2 front/back boundaries and reduce current-path density.

Properties of GaN grown on Si(111) substrates dependent on the thickness of 3C-SiC intermediate layers

Crack-free GaN epilayers were grown with the mask less epitaxial lateral overgrowth (ELO) on Si substrates with various thicknesses of 3C-SiC intermediate layers. The defects in 3C-SiC and GaN layers were studied to reveal the impact of 3C-SiC intermediate layer on GaN epitaxy. In the 3C-SiC layer, a gradient density of stacking faults (SFs) was observed along the growth direction. Most of the SFs locate in the first 500-nm-thick 3C-SiC layer. Thanks to the maskless ELO method, the defects in under layer could not extend into GaN layer, even grown on a 100-nm-thick 3C-SiC layer with high density. The threading dislocation density in GaN varies in the range of ∼(1 ± 0.3) × 109 cm−2. Investigation of GaN nucleation indicated a correlation between GaN quality and surface roughness of 3C-SiC layers. Meanwhile, the surface morphology of 3C-SiC is affected by double positioning domains, which revealed as a result of strain relaxation process during growth on Si substrate.

Elimination of square pits on SIMOX wafer by using nitrogen-doped Cz crystal

Recent developments in LSI technology require SOI wafers for realization of higher speed operation and lower power consumption. SIMOX wafers are one of the leading SOI wafer materials, and have been revealing high performance such as excellent SOI layer thickness uniformity, even below the 0.1 /spl mu/m thickness range which is required for CMOS applications. To realize high device performance, a defect-free SOI surface is desirable, especially for achieving superior gate oxide integrity (GOI). While the GOI on the SIMOX wafers fabricated by the internal thermal oxidation (ITOX) process was reported to be superior to that on the conventional Cz wafers (Kawamura et al, 1996), it was reported that crystal originated particle (COP)-like pits exist on standard SIMOX wafers (Naruoka et al, 1997), although their origin has not been clearly resolved. In this study, we investigated the pits on ITOX-SIMOX wafers fabricated on various starting materials with different COP density. The influence of COPs in the starting materials on the pits on the SIMOX wafers was discussed and the possibility of pit-free SIMOX using nitrogen-doped Cz crystals was illustrated.

Gate oxide integrity on ITOX-SIMOX wafers

The Gate-Oxide-Integrity (GOI) on Thin-Film-Silicon-On-Insulator (TFSOI) wafers is required to be the same as that on bulk silicon wafers in a commercial stage of LSIs using SOI CMOS technology. However, the GOI on TFSOI wafers, especially charge-to-breakdown characteristics, has been reported to be inferior to that on bulk wafers. In this paper, the GOI on ITOX (Internal-Thermal-OXide)-SIMOX wafers fabricated by the low-dose implanting and High-Temperature-Oxidation (HTO) technique is investigated, revealing that ITOX-SIMOX wafers have GOI comparable to that on bulk wafers. The influence of device structures, particularly of total gate edge length, on the GOI is also discussed.

An analysis of buried-oxide growth in low-dose SIMOX wafers by high-temperature thermal oxidation

The buried-oxide (BOX) growth by a high-temperature thermal oxidation of low-dose SIMOX wafers is becoming an indispensable technique for the improvement of material quality, for example, surface roughness and BOX leak path density, as well as the slight decrease in the parasitic capacitance. The physical mechanism of the BOX growth by a thermal oxidation has been investigated for bonded wafers oxidized at 1100/spl deg/C; however, the typical oxidation temperature for low-dose SIMOX wafers is much higher than 1100/spl deg/C. To clarify the oxidation mechanism at higher temperatures and predict the thermally-grown BOX thickness for various conditions, we explore the oxidation process with a simple model based on Deal and Groves analysis.