Keith A. Campbell

Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles

Post-silicon validation and debug challenges of system-on-chips (SoCs) are getting increasingly difficult. As we reach the limits of Dennard scaling, efforts to improve system performance and energy efficiency have resulted in the integration of a wide variety of complex hardware accelerators in SoCs. Hence, it is essential to address post-silicon validation and debug of hardware accelerators. High-level synthesis (HLS) is a promising technique to rapidly create customized hardware accelerators. In this paper, we present the Hybrid Quick Error Detection (H-QED) approach that overcomes post-silicon validation and debug challenges for hardware accelerators by leveraging HLS techniques. H-QED improves error detection latencies (time elapsed from when a bug is activated to when it manifests as an observable failure) by 2 orders of magnitude and bug coverage 3-fold compared to traditional post-silicon validation techniques. H-QED also uncovered previously unknown bugs in the CHStone benchmark suite, which is widely used by the HLS community. H-QED incurs less than 2% chip-level area overhead with negligible performance impact, and we also introduce techniques to minimize any possible intrusiveness introduced by H-QED.

High-level Synthesis for Low-power Design

Power and energy efficiency have emerged as first-order design constraints across the computing spectrum from handheld devices to warehouse-sized datacenters. As the number of transistors continues to scale, effectively managing design complexity under stringent power constraints has become an imminent challenge of the IC industry. The manual process of power optimization in RTL design has been increasingly difficult, if not already unsustainable. Complexity scaling dictates that this process must be automated with robust analysis and synthesis algorithms at a higher level of abstraction. Along this line, high-level synthesis (HLS) is a promising technology to improve design productivity and enable new opportunities for power optimization for higher design quality. By allowing early access to the system architecture, high-level decisions during HLS can have a significant impact on the power and energy efficiency of the synthesized design. In this paper, we will discuss the recent research development of using HLS to effectively explore a multi-dimensional design space and derive low-power implementations. We provide an in-depth coverage of HLS low-power optimization techniques and synthesis algorithms proposed in the last decade. We will also describe the key power optimization challenges facing HLS today and outline potential opportunities in tackling these challenges.

High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths

In this study, we propose a low-cost approach to error detection for arithmetic orientated data paths by performing lightweight shadow computations in modulo-3 space for each main computation. By leveraging the binding and scheduling flexibility of high-level synthesis, we detect errors through diverse binding and minimize area cost through intelligent checkpoint scheduling and modulo-3 reducer sharing. We evaluated our technique with 12 high-level synthesis benchmarks using FPGA emulated netlist-level error injection. We observe coverages of 99.13% for stuck-at faults, 99.46% for soft errors, and 99.67% for timing errors with a 25.7% area cost and negligible performance impact. Leveraging error detection latencies on the order of 10 cycles (3 orders of magnitude faster than end result check) for soft errors, we also explore a rollback recovery method with an additional area cost of 28.0%, observing a 175x increase in reliability against soft errors.

Debugging and verifying SoC designs through effective cross-layer hardware-software co-simulation

Verification of modern day electronic circuits has become the bottleneck for the timely delivery of complex SoC designs. We develop a novel cross-layer hardware/software co-simulation framework that can effectively debug and verify an SoC design. We combine high-level C/C++ software with cycle-accurate SystemC hardware, uniquely identify various types of bugs, and help the hardware designer localize them. Experimental results show that we are able to detect and aid in localization of logic bugs from both C/C++ specifications as well as the high-level synthesis engine itself. Our framework is fully automated, representing an important step forward targeting fast and effective SoC design verification.

Designing high-quality hardware on a development effort budget: A study of the current state of high-level synthesis

High-level synthesis (HLS) promises high-quality hardware with minimal development effort. In this paper, we evaluate the current state-of-the-art in HLS and design techniques based on software references and architecture references. We present a software reference study developing a JPEG encoder from pre-existing software, and an architecture reference study developing an AES block encryption module from scratch in SystemC and SystemVerilog based on a desired architecture. Additionally, we develop micro-benchmarks to demonstrate best-practices in C coding styles that produce high-quality hardware with minimal development effort. Finally, we suggest language, tool, and methodology improvements to improve upon the current state-of-the-art in HLS.

Cross-Layer Resilience in Low-Voltage Digital Systems: Key Insights

CLEAR (Cross-Layer Exploration for Architecting Resilience) is a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to hardware errors: achieve desired resilience targets at low cost (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). CLEAR automatically and systematically explores the large space of resilience techniques and their combinations, derives cost-effective solutions, provides guidelines for designing new techniques, and offers insights into how to design cost-effective digital systems resilient to hardware errors: 1. circuit-level techniques are crucial; 2. application-level guidance is essential; 3. existing architecture and software techniques are generally expensive or provide too little resilience; 4. some previously published techniques suffer from inaccurate analysis, leading to incorrect conclusions; 5. cost-effective protection from multiple error sources is achieved by combining techniques targeting each specific error source.

New advances of high-level synthesis for efficient and reliable hardware design

Abstract The spectacular CMOS technology scaling will continue to evolve and dominate the semiconductor industry. This will lead to tens of billions of transistors integrated on a single chip by the year 2020. However, one significant problem is that the design productivity for complex designs has been lagging behind. In addition to several proposed techniques for dealing with the widening productivity gap, e.g., IP reuse and integration, virtual platform modeling, formal verification and others, high-level synthesis (HLS) has been touted as an important solution as it can significantly reduce the number of man-hours required for a design by raising the level of design abstraction. However, existing HLS solutions have limitations, and studies show that the design quality of HLS can be inferior compared to that of manual RTL design. In this paper, we will present a set of new techniques developed recently to drastically improve HLS solutions, which not only improve the traditional design metrics such as circuit performance and energy efficiency but also emerging metrics such as hardware security and robustness. We will also discuss how HLS can collaborate with other techniques to provide a holistic design methodology that can enable the delivery of high-quality designs with much less design cost and much faster time-to-market.