Keith Bryan Hardin

Spread spectrum clock generation for the reduction of radiated emissions

A method is presented for reducing the radiated emissions of an electronic device by frequency modulating (FM) the system clock. This method, referred to as spread spectrum clock generation, or SSCG, is applicable to most microprocessor based systems. A unique waveform used to frequency modulate a digital clock signal results in a spectrum with sideband harmonics that are nearly uniform in amplitude when measured with an EMI receiver. This has the effect of spreading the energy of a discrete frequency harmonic over a wider bandwidth, thereby reducing the amplitudes of the harmonics. Attenuation as high as 13 dB is presented using an experimental setup, an actual SSCG integrated circuit, and theoretically computed results.<<ETX>>

Investigation into the interference potential of spread-spectrum clock generation to broadband digital communications

Since its inception, spread-spectrum clocks have been a valuable technology for the purposes of EMI reduction and EMC compliance. This study evaluates the interference potential of spread spectrum clocks to broadband digital communications such as high definition television (HDTV). This is accomplished by comparing the spread spectrum clock interference susceptibility of digital television (DTV) receivers to the interference susceptibility of analog television receivers. This study shows that DTV receivers are more immune to the same level of interference than existing analog television receivers by 16 dB. Since industry has shown that analog television has had negligible interference from information technology equipment, including spread spectrum clocks, then the digital systems should have even less.

Design considerations of phase-locked loop systems for spread spectrum clock generation compatibility

A technique was proposed which reduces the radiated emissions of a digital clock signal and its associated harmonics by as much as 10-20 dB, depending on frequency. This technique, referred to as spread spectrum clock generation (SSCG), reduces the radiated emissions associated with a clock signal by modulating the signal with a unique waveform. This technique can be used with minimal consideration when used in a system that does not utilize frequency dependent devices such as a phase-locked loop (PLL). For those designs which incorporate a PLL, attention must be given to the design of the PLL in order to minimize clock skew while at the same time maintain maximum attenuation of emissions. This paper presents design considerations and modeling techniques that an EMC engineer should consider when implementing SSCG in PLL based systems.

A study of the interference potential of spread spectrum clock generation techniques

A technique to reduce the radiated emissions of digital clock signals and associated harmonics has previously been presented (Hardin et al. 1994). This technique, referred to as spread spectrum clock generation, or SSCG, intentionally broadbands a normally narrowband signal by frequency modulating the trapezoidal clock signal with a unique modulating waveform. As a result of this modulation, the amplitudes of the harmonics of the clock signal can be reduced by as much as 2-22 dB, depending on the frequency of measurement and the frequency deviation. Since the decrease in the amplitudes of the clock harmonics is accomplished by increasing the bandwidth occupied by the harmonics, a number of SSCG clock harmonics may correspond in frequency to an intentionally transmitted signal, such as radio or television. This raises the question of whether SSCG clock generation techniques result in an increase in the interference potential to wideband broadcast receivers as compared to existing clock generation techniques. An additional question which arises is whether existing electromagnetic interference (EMI) measurement procedures are appropriate for products utilizing this technology. The paper presents experimental studies of the interference characteristics of SSCG to broadcast receivers, in particular to television receivers. The results indicate that SSCG presents no greater interference potential to television receivers and in the case of the television audio quality, creates significantly less interference than standard clock generation techniques and that existing EMI measurement procedures are appropriate.

Decomposition of radiating structures using the ideal structure extraction methods (ISEM)

A method for decomposing an asymmetrical structure into two substructures is given. One substructure contains the attributes of symmetry while the remainder or residual substructure contains the attributes of asymmetry. The decomposition is done in such a way that the superposition of the radiated electromagnetic fields of the decomposition substructures gives the radiated fields of the original structure. Although the substructures can, by superposition, be used to compute the total radiated fields of the original structure, the primary purpose of the decomposition technique is to provide insight into methods for reducing the emissions of each substructure and consequently those of the original structure. In many cases the emissions of the asymmetric substructure are the dominant contributors to the total emissions of the original structure. In this case, the decomposition substructures allow direct insight into the reduction of the total emissions that was previously available only for the symmetric substructure. >

Broadband measurement of near-fields for predicting far-fields for EMC applications

The objective of this effort is to further the fundamental understanding of radiated noise emissions from consumer electronic products. A phase and time coherent method for measuring the near-fields of a device given wideband-radiating sources is used. Site sources normally used to verify chambers are chosen for this research. The design and characterization of near-field probes to perform simultaneous E-and H-field measurements is presented. A fast Fourier transform based near-field to far-field transformation of the planar near-field data is implemented. HFSSTM (High Frequency Structure Simulator) simulations are used as benchmark for this study.

Prediction of crosstalk due to showering arcs at switch contacts

The modeling and prediction of crosstalk in automotive wiring harnesses that is due to arcing at the contacts of mechanical switches are addressed. A model of the showering arc phenomenon at a switch contact is developed. This model is suitable for implementation in CAD codes such as SPICE, PSPICE, and PRECISE. The crosstalk is modeled using lumped-parameter circuits (lumped-pi). Experimental results are shown which validate the model and also indicate the severe crosstalk that can be produced by this showering arc.<<ETX>>

A novel z-directed embedded component for the reduction of voltage ripple on the power distribution network for PCBs

A new capacitor package and PCB embedding technique is introduced to significantly reduce the system power distribution network impedance at the pads of surface mounted integrated circuits. The capacitor is multi-layer ceramic capacitor (MLCC) that is a right cylindrical shape with via channels in the outer wall along the axis of the part. The capacitor called a Z-Directed component (ZDC) is then pressed into a hole in the PCB. The connections to the component are then made by the copper plating process similar to via hole construction. This new configuration dramatically improves the PDN performance of PCBs with fewer components than the conventional solution with SMD decoupling capacitors.

A novel Z-directed embedded component for the reduction of voltage ripple on the power distribution network for PCBs

A new capacitor package and PCB embedding technique is introduced to significantly reduce the system power distribution network impedance at the pads of surface mounted integrated circuits. The capacitor is multi-layer ceramic capacitor (MLCC) that is a right cylindrical shape with via channels in the outer wall along the axis of the part. The capacitor called a Z-Directed component (ZDC) is then pressed into a hole in the PCB. The connections to the component are then made by the copper plating process similar to via hole construction. This new configuration dramatically improves the PDN performance of PCBs with fewer components than the conventional solution with SMD decoupling capacitors.