Ken A. Nishimura

Design and performance of a reconfigurable liquid-crystal-based optical add/drop multiplexer

The authors describe a reconfigurable optical add-drop multiplexer designed for 50-GHz channel spacing over either the C- or L-bands. The system may also function as a variable optical attenuator. The design features a reflective liquid-crystal modulator, a compact free-space spectrometer, polarization diversity, and fine-scale attenuation control.

XGA resolution full-video microdisplay using light-emitting polymers on a silicon active matrix circuit

Capable self-emissive polymers are being developed for use as emitting materials for a variety of display applications. This paper describes the use of standard CMOS integrated circuit silicon wafer technology along with a spin-cast polyfluorene-base polymer emissive layer, to demonstrate an XGA resolution, full video microdisplay. The silicon chip drive circuitry (Analog Pixel-APIX) is described along with results from our efforts to optimize the reflective anode, the semitransparent cathode process, and emissive cell construction. The 1024 X 768 pixel display achieves 200 Cd/m2 brightness at low power (<50 mW) with fast 1 usec response times. In addition, we summarize future directions to achieve color and the need to incorporate a production- worthy seal layer on microdisplays manufactured on silicon wafers.

An 8.2 to 20.1 GHz LC PLL with Sub-100 fs Jitter in 0.13 µm SiGe BICMOS

A dual-path PLL comprising two LC VCOs covers a tuning range from 8.2 to 20.1 GHz. Able to operate with a wide range of feedback-divider ratios (N), the PLL provides a total jitter of 65.3 fsrms when N=2 and 206.1 fsrms when N=16. In addition, the PLL achieves loop bandwidths up to 100 MHz which enables it to be used as a clean-up PLL at the receiver. In order to provide low jitter and low reference spurs for a wide range of reference frequencies, a novel architecture that uses switched multi-pole spur-reduction filters with dedicated phase detectors is introduced. The spur levels at the output are -55 dBc and -62 dBc when N=2 and N=16, respectively. Implemented in a 0.13 μm SiGe BiCMOS process, the 1.31 mm2 PLL dissipates a total of 302 mW from 1.2 V and 2.5 V supplies.

EP2: Anatomy of innovation: Bug or feature?

As process scaling slows down, circuit innovation is becoming one of the most important differentiators. We can point to great inventions of the past that were accidental, or failed attempts to solve other problems (bugs), as well as those from logical thinking (features). Which is more effective? In this panel, top analog circuit innovators describe the process by which their best innovations were conceived. They give interesting examples, such as turning a bug in the circuit into a feature. Then they argue whether innovation is more effective as a result of accidental discovery or logical thinking.

8-bit/color 1024/spl times/768 microdisplay with analog in-pixel pulse width modulation and retinal averaging offset correction

A liquid-crystal-on-silicon microdisplay based on a 1024/spl times/768 2-D pixel array fabricated in a digital 0.35 /spl mu/m CMOS process displays images with a color depth of 8-bits/color. The pixel pitch is 22 /spl mu/m and the total chip area is 214 mm/sup 2/. Pixel brightness is controlled by modulating the pulse width of the pixel voltage drive signal with an in-pixel analog pulse width modulation (PWM) circuit which utilizes human optic nerve spatio-temporal averaging to eliminate comparator offset. The 16 million transistor chip displays images at a maximum rate of 85 Hz and has a power dissipation of 200 mW from a single 3.3 V supply.