Kenichi Hase

A BiCMOS PLL-based data separator circuit with high stability and accuracy

A data separator that can work in Winchester disk drives at a read/write speed of up to 30 Mb/s is described. To realize high stability and accuracy in reproducing data in high-speed transfers, a digital synchronization field detector and an analog dual-mode phase-locked loop (PLL) that has a phase detector which has constant gain in the data field, independent of pattern, are used. The dual-mode analog PLL has a wide decode margin, locks up quickly, and operates stably without being affected by the frequency deviation of data. The digital sync field detector is adjustment-free and detects sync fields very accurately. The IC incorporates a RLL 2-7 code encoder/decoder and a write compensator. Use of the 2- mu m BiCMOS process keeps the total power consumption as low as 400 mW even at the high transfer rate of 30 Mb/s. >

A 32 Mb/s disk drive data separator for constant density recording

The authors describe a data separator LSI that has been developed for use in hard disk drives for constant density recording. The data separator LSI has a built-in read clock pulse recovery PLL (phase-locked loop) and write clock pulse generator PLL that can divide and program transfer rates with double frequency range into 32 steps. The COV has a clock pulse jitter of 0.4 ns and functions for switching center frequencies so that it can handle all transfer rates. The read clock pulse recovery PLL, required for especially critical programming of constants, divides programmable transfer rates into two groups, one for low speeds and the other for high speeds, and it has functions for independent programming of natural frequency and damping factor. Use of the 2- mu m BiCMOS process allows data coding and decoding at a maximum speed of 32 Mb/s and a power consumption of 440 mW.<<ETX>>

A gain-controlled integrator technique for a 50 MHz, 100 mW, 0.4 /spl mu/m CMOS, 7th-order equiripple G/sub m/-C filter

This gain-controlled integrator technique generates high-precision, high-speed, low-voltage G/sub m/-C filters. Cut-off frequency (fc) must be tunable between 50 - 100MHz. Group delay variation ±5% of l/fc over the full fc range is required for linear phase response. A 7th-order 0.05° equiripple filter with three quadratic sections and a one-pole low-pass section is used for its inherently low group delay variation. For precise equiripple filter characteristics, the quality factor (Q) and pole-frequency (fp) must coincide with their specified values over the full fc variable range.