Kenichi Maeda

Towards 3-Dimensional Pattern Recognition

3-dimensional pattern recognition requires the definition of a similarity measure between 3-dimensional patterns. We discuss how to match 3-dimensional patterns, which are represented by a set of images taken from multiple directions and approximately represented by subspaces. The proposed method is to calculate the canonical angles, in particular the third smallest angle between two subspaces. We demonstrate the viability of the proposed method by performing a pilot study of face recognition.

From the Subspace Methods to the Mutual Subspace Method

The Subspace Method [25, 21] is a classic method of pattern recognition, and has been applied to various tasks. The Mutual Subspace Method [19] is an extension of the Subspace Methods, in which canonical angles (principal angles) between two subspaces are used to define similarity between two patterns (or two sets of patterns). The method is applied to face recognition and character recognition in Toshiba Corporation. The Karhunen-Lo‘eve eigenvalue method or Principal Component Analysis (PCA) [8, 13, 17] is a well-known approach to form a subspace that approximates a distribution of patterns, and it was introduced as a tool of pattern recognition [10, 24]. The extension from the Subspace Methods to the Mutual Subspace Method corresponds to the difference between PCA and Canonical Correlation Analysis (CCA) [9]. In this chapter, the Mutual Subspace Method, its mathematical foundations and its applications are described.

ISAR image analysis by subspace method: automatic extraction and identification of ship profile

This paper deals with automatic identification of ships in images produced by inverse synthetic aperture radar (ISAR). The ISAR technique reconstructs a rapidly updating sequence of range-Doppler image frames of the target. Due to the physics of imaging based on the targets angular motions, however, images are invariably noisy, and not all frames contain equally useful information. The thrust of this research is to cope with these issues by introducing: (i) a multiframe algorithm to stably extract profiling as a basic feature reflecting the entire characteristics of a target; and (ii) subspace analysis for identification of the extracted profiling especially using the recently proposed constrained mutual subspace method (CMSM). Through preliminary experiments we demonstrate the effective performance of the proposed scheme.

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension

Mobile devices have made remarkable advances in recent years. They generally use embedded NAND storage devices, which are tiny (10s of millimeters square) and low-power (around 1W in the active state) single BGA packages that contain both a controller and NAND chips. Figure 19.3.1 shows read performance of recent embedded NAND storage device products and the maximum link speeds in their standards. The figure indicates that more powerful embedded NAND storage devices are desired by the market. In particular, universal Flash storage (UFS) 2.0, the latest standard, defines high link speed, which is 3× faster than the recent embedded multimedia card (eMMC). In this context, we develop a UFS 2.0 device that introduces new features to the conventional embedded NAND storage device controller architecture to improve read performance. Figure 19.3.2 shows a block diagram of our controller. We improve the read performance in the following ways: 1) suppress the number of NAND read accesses and reduce the read latency by introducing unified memory (UM) and caching data for address translations on it, 2) increase the number of NAND chips activated simultaneously with dedicated hardware and new command scheduling, and 3) maximize bandwidth by supporting 5.8Gb/s 2-lane M-PHY link with low-power analog circuits.

Caching mechanisms towards single-level storage systems for Internet of Things

Internet of Things (IoT) involves coping with enormous number of distributed devices. This paper introduces three pieces of caching technology as steps towards single-level storage systems that can host and map numerous IoT devices on a single vast address space: 1) a caching mechanism for making solid-state storage appear as huge main memory, 2) speeding up access to resource-limited IoT devices by caching the address translation table of solid-state storage chips, and 3) ad hoc device-to-device data relay, which can be used as effective network caching for mapping IoT devices.

Real and simulator testbeds for content dissemination in high-density large-scale WANET

A wireless ad hoc network (WANET) is an effective approach to disseminating digital content without the need for infrastructure networks. It is not only useful in the absence of commodity connections such as cellular networks, but also useful for avoiding overloading those connections in crowded scenarios, an example of which is delivering movie clips throughout spectators in a stadium. However, experiments of WANET have been oftentimes conducted using only up to 1,000 nodes in a simulator or dozens of real devices, both typically scattered across a wide area at a density of around 10−4 node/m2. This paper focuses on the problem of disseminating common content to all the devices in the same area via 802.11-based WANET, and presents a pair of testbeds, one based on real devices and the other a simulator, both capable of high-density and large-scale experiments with roughly matched performance. We have found naive implementation of content dissemination protocols alone not to work in high density, and we identify necessary adjustment of wireless parameters to allow for experiments even with an extreme density of 20 nodes/m2. We show that 2.5 MB of data can be delivered to 100 real devices and to 10,000 simulated devices in a few minutes on our testbeds, demonstrating the feasibility of orders of magnitude larger-scale experiments.

Twin-register architecture for an AI processor

Abstract We have developed a twin-register architecture to improve the backtracking speed of Prolog programs. The twin-register architecture is designed to realize a virtual infinite register set. The features of the architecture are: (1) only a small amount of hardware is needed including a pair of register-files; and, (2) data transfer between the register and the memory is automatically executed. A register saving/restoring operation and the Prolog instruction are executed in parallel in order to reduce the overhead of memory accesses. We have implemented the twin-register architecture into our AI processor IP704 to show its effectiveness. Experimental results have shown that the execution time of 8-Queen program is reduced by 15% in the case of the twin-register architecture, as compared with that in the case of the ordinary architecture in which saving/restoring are done by software. Also, we have found the architecture is useful for register saving/restoring of the procedure CALL/RETURN in general procedural programs.

Twin register architecture for an AI processor

A twin register architecture has been developed to improve the backtracking speed of Prolog programs. The twin register architecture is intended to realize a virtual infinite register set. The features of the architecture are: (1) only a small amount of hardware is needed, including a pair of register files, and (2) data transfer between the register and the memory is automatically executed. A register saving/restoring operation and the Prolog instruction are executed in parallel to reduce the overhead of memory accesses. The twin register architecture has been implemented in the IP704 AI processor to determine its effectiveness. Experimental results have shown that the execution time of the 8-Queen program is reduced by 15% in the case of the twin register architecture as compared with that for the ordinary architecture, in which saving/restoring are done by software. Also, the architecture is useful for register saving/restoring of the CALL/RETURN procedure in general procedural programs.<<ETX>>