Kenichi Takatori

6.3: Field-Sequential Smectic LCD with TFT Pixel Amplifier

A field-sequential color smectic LCD has been developed using low-temperature poly-Si TFTs. An active-load type TFT pixel amplifier is used to drive a V-shaped-switching smectic LC without voltage fluctuation. The optical response time is 300 μs for a field frequency of 180 Hz. This LCD is capable of displaying high-quality motion-picture images.

46.3: DRAM‐Frame‐Memory Embedded SOG‐LCD

An SOG-LCD with integrated 230kb DRAM frame memory has been demonstrated. To achieve this dense integration, a memory system architecture for horizontal stripe was developed. Memory tests proved a 1MHz operation and retention time of 166ms. Fine images are displayed both in still images and moving pictures.

A complementary TN‐LCD with wide‐viewing‐angle gray scale

— A complementary TN (C-TN) structure with two domains based on a simple fabrication process is proposed. To fabricate this C-TN cell, only one photolithography process and one rubbing process are added to conventional TN fabrication processes. This C-TN cell has symmetrical transmittance in the up and down directions. The gray-level order in the C-TN cell is maintained within a four-times-wider viewing angle than that in a conventional TN cell.

45.1: Touch Panel Embedded IPS‐LCD with Parasitic Current Reduction Technique

A capacitive-type touch-panel-embedded IPS-LCD is realized by novel parasitic current reduction technique (PCR). The PCR removes 90% of the current flowing through the parasitic capacitance on a capacitive sensor (ITO layer) formed on a color filter substrate. Since the IPS-LCD has the same structure as commercial products, it features no reduction in aperture ratio.

29.3: A 1450-ppi Field-Sequential System-on-Glass LCD Capable of Operating Over a Wide Temperature Range

We succeeded in developing a field-sequential color system-on-glass (SOG) LCD with a twisted-nematic mode using a novel material and novel driving method. We achieved a 4-ms response time and operation over a wide range of temperatures with a 2.1-μm cell gap. High optical efficiency was demonstrated with an aperture ratio of 59% and a 17.5-μm pixel pitch.

A two dimensional liquid crystal simulation for thin film transistor liquid crystal displays

Abstract A two-dimensional liquid crystal simulation, whose electrode configuration corresponds to that in a thin film transistor liquid crystal display (TFT-LCD), was carried out. Simulation results show that the lateral field between buslines and pixel electrode forms a reverse tilt domain. This reverse tilt domain leads to the disclination on the pixel electrode. The distance from the pixel electrode edge to this disclination location depends on the dielectric anisotropy and elastic constant for the liquid crystal. A small dielectric anisotropy or large elastic constant makes this distance small.

62.3: A Non‐Rectangular Heart‐Shaped SOG‐LCD

A non-rectangular SOG-LCD has been developed by a well-polished system-integration technology including an arrangement in space. Driver circuits integrated along with curved sides of a heart-shaped screen with a hollow and an array of pixels slanting 45 degrees offer narrow bezels of less than 2 mm.

Back- and Front-Interface Trap Densities Evaluation and Stress Effect of Poly-Si TFT

The polycrystalline silicon (poly-Si) TFT has two insulator interfaces between the polycrystalline silicon and front and back insulators. These interfaces have trap states, which affect the characteristics of poly-Si TFT. In the silicon-on-insulator (SOI) technology area, using the dual-gated, fully-depleted SOI MOSFET under the depleted back-channel condition, the back-interface trap density can be calculated through the front-channel threshold voltage and film thicknesses. The front-interface trap density is also evaluated changing the roles of both gates. This evaluation method for front- and back-interface trap densities is called the threshold-voltage method. To apply this threshold-voltage method to the “medium-thickness” poly-Si TFT, of which the channel is not fully depleted in normal single gate bias operation, the biases for both front and back gates are controlled to realize full depletion. Under the fully-depleted condition, the front- or back-threshold voltage of poly-Si TFT is carefully extracted by the second-derivative method changing back- and front-gate biases. We evaluated the front- and back-interface trap densities not only for normal operation but also under stress. To evaluate the bias and temperature stress effect, we used two types of samples, which are made by different processes. The evaluated front- and back-interface trap densities for both samples in initial state are around 5×1011 to 1.3×1012cm-2eV-1, which are almost the same as the reported values. Applying bias and temperature stress shows the variation of these interface-trap densities. Samples with large shifts of the front-channel threshold voltage show large trap density variation. On the other hand, samples with small threshold voltage shifts show small trap density variation. The variation of the back-interface trap density during the stress application showed a correlation to the front-channel threshold voltage shift.

Splayed TN Configuration Stability in Domain-Divided TN Mode

Abstract In the domain-divided TN mode for a wide-viewing-angle LCD, the LC directors are arranged in the splayed TN configuration by mismatching the pretilt directions on both substrates. For this mismatched pretilt alignment, the splayed TN configuration and the is shown that the reversely-twisted TN configuration are possible. It is more stable than the splayed TN in the high voltage range. The splayed TN stability proved to be evaluated by the balanced voltage, defined as voltage at which LC bulk energy becomes equal for two configurations in a simulation or voltage at which the boundary between two configurations is fixed in an experiment. Narrow twist angle, short chiral pitch and low pretilt angles raise the balanced voltage, i.e., stabilize the splayed TN configuration.