Kenichiro Hirose

Delay-Compensation Flip-Flop with In-situ Error Monitoring for Low-Power and Timing-Error-Tolerant Circuit Design

With the continuous downscaling of transistors, process variation and power consumption have become major issues. Dynamic voltage and frequency scaling (DVFS) with in-situ timing-error monitoring is an effective method that addresses both issues. However, the conventional implementations of this method, which are mainly based on duplicated circuits, have some implementation-specific constraints. In this paper, the authors propose a delay-compensation flip-flop (DCFF) that does not use duplicated circuit components. It monitors timing errors by directly checking the transient timings of signals. The DCFF adjusts the rising-edge timings of the clock to avoid timing errors and compensates the timing margins between successive stages. Simulations using simulation program with integrated circuit emphasis (SPICE) indicated that the DCFF can operate in a wider supply voltage range than the conventional implementation of DVFS with in-situ timing-error monitoring. A 2.5 ×2.5 mm2 test chip was designed by using a 0.18 µm 5-metal process. An essential circuit component of the DCFF was implemented using semi-custom gate-array chips and its operation was verified. Although more detailed and varied simulations and actual measurements are required as future work, DCFFs can be effectively applied to process-variation tolerance and low-power computation and to optimize the design margin and resolve the false-path problem.

A simultaneous vertical and horizontal self-patterning method for deep three-dimensional microstructures

This paper proposes a self-patterning method for simultaneous vertical and horizontal patterning of µm scale three-dimensional structures. Only a directional deposition such as evaporation and sputtering over a sidewall- profile-controlled structure completes the patterning of the deposited material. The three-dimensional self-patterning structure is made with a simple resist-exposure technique combined with sidewall-profile- controlled deep reactive ion etching. This method is useful for the fabrication of microelectromechanical systems and semiconductor devices which need lithography on the sidewall and bottom of the deep trenches, or which use materials not compatible with the conventional lithography process. As an application of this method, a 60 µm × 40 µm solenoid-type vertically buried inductor was fabricated, by aluminum evaporation of the profile-controlled three-dimensional structure.

Polarization-Transmissive Thin-Film Solar Cell with Photodiode Nanowires

The polarization-transmissive thin-film solar cell, which consists of a 400 nm-wide silicon photodiode-nanowire grid, transmits the light polarized in one direction and generates photocurrent from the light polarized in the other direction. It can efficiently use light in the system which uses polarization. The fabricated device generated 52 nA photocurrent from the 250 muW incident light by a fluorescent light and achieved the extinction-ratio of 4 for the incident light whose wavelength was 675 nm.

Delay-Compensation Flip-Flops for Timing-Error Tolerant Circuit Design

1. Introduction As the clock frequency and circuit integrity have been increased exponentially, power consumption has also increased drastically and process variations have been becoming a big issue. One of the most effective methods for low power computation is dynamic voltage scaling (DVS) with in-situ timing-error detection. Furthermore, it is robust to parameter variations in the extremely scaled technology generations and can minimize timing and voltage margins, because supply voltage is dynamically tuned during circuit operation, or after every fabrication process is finished. However, conventional methods for in-situ timing-error monitoring have some disadvantages: the decrease of the degree of freedom for designing circuits and the necessity of the complex recovery mechanism for timing errors. The delay-compensation flip-flop (DCFF) automatically regulates its control signal as it finds the boundary between two successive data with error detection. The purpose of this paper is to present how DCFF can substantially improve the problems mentioned above, compared to conventional methods described in the section 2.