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Dive into the research topics where Kenichiro Yoshii is active.

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Featured researches published by Kenichiro Yoshii.


international solid-state circuits conference | 2014

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension

Konosuke Watanabe; Kenichiro Yoshii; Nobuhiro Kondo; Kenichi Maeda; Toshio Fujisawa; Junji Wadatsumi; Daisuke Miyashita; Shouhei Kousai; Yasuo Unekawa; Shinsuke Fujii; Takuma Aoyama; Takayuki Tamura; Atsushi Kunimatsu; Yukihito Oowaki

Mobile devices have made remarkable advances in recent years. They generally use embedded NAND storage devices, which are tiny (10s of millimeters square) and low-power (around 1W in the active state) single BGA packages that contain both a controller and NAND chips. Figure 19.3.1 shows read performance of recent embedded NAND storage device products and the maximum link speeds in their standards. The figure indicates that more powerful embedded NAND storage devices are desired by the market. In particular, universal Flash storage (UFS) 2.0, the latest standard, defines high link speed, which is 3× faster than the recent embedded multimedia card (eMMC). In this context, we develop a UFS 2.0 device that introduces new features to the conventional embedded NAND storage device controller architecture to improve read performance. Figure 19.3.2 shows a block diagram of our controller. We improve the read performance in the following ways: 1) suppress the number of NAND read accesses and reduce the read latency by introducing unified memory (UM) and caching data for address translations on it, 2) increase the number of NAND chips activated simultaneously with dedicated hardware and new command scheduling, and 3) maximize bandwidth by supporting 5.8Gb/s 2-lane M-PHY link with low-power analog circuits.


Archive | 2004

Method and system for performing real-time operation

Tatsunori Kanai; Seiji Maeda; Hirokuni Yano; Kenichiro Yoshii


Archive | 2002

DATA TRANSFER SCHEME USING CACHING AND DIFFERENTIAL COMPRESSION TECHNIQUES FOR REDUCING NETWORK LOAD

Tatsunori Kanai; Toshibumi Seki; Kenichiro Yoshii; Hideaki Sato; Takayuki Miyazawa; Haruhiko Toyama; Yasuhiro Kimura; Hideki Yoshida


Archive | 2002

Data transfer scheme using caching technique for reducing network load

Toshibumi Seki; Tatsunori Kanai; Kenichiro Yoshii; Hideki Yoshida; Haruhiko Toyama; Hideaki Sato; Yasuhiro Kimura; Takayuki Miyazawa


Archive | 2011

Semiconductor memory controlling device

Shigehiro Asano; Shinichi Kanno; Kenichiro Yoshii


Archive | 2003

Task allocation method in multiprocessor system, task allocation program product, and multiprocessor system

Kenichiro Yoshii; Hirokuni Yano; Seiji Maeda; Tatsunori Kanai


Archive | 2004

Method and system for performing real-time operation using processors

Tatsunori Kanai; Seiji Maeda; Kenichiro Yoshii; Hirokuni Yano


Archive | 2011

Controller, data storage device and program product

Kazuhiro Fukutomi; Kenichiro Yoshii; Shinichi Kanno; Shigehiro Asano


Archive | 2003

Computer system, computer device, and method and program for migrating operating system

Takuya Hayashi; Seiji Maeda; Kiyoko Satou; Hirokuni Yano; Kenichiro Yoshii; 記代子 佐藤; 誠司 前田; 謙一郎 吉井; 拓也 林; 浩邦 矢野


Archive | 2003

Data transfer scheme for reducing network load using general purpose browser on client side

Yuichi Koba; Yasuhiro Kimura; Kenichiro Yoshii; Atsushi Shono; Hideaki Sato; Toshibumi Seki

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