Kenichiro Yoshii

19.3 66.3KIOPS-random-read 690MB/s-sequential-read universal Flash storage device controller with unified memory extension

Mobile devices have made remarkable advances in recent years. They generally use embedded NAND storage devices, which are tiny (10s of millimeters square) and low-power (around 1W in the active state) single BGA packages that contain both a controller and NAND chips. Figure 19.3.1 shows read performance of recent embedded NAND storage device products and the maximum link speeds in their standards. The figure indicates that more powerful embedded NAND storage devices are desired by the market. In particular, universal Flash storage (UFS) 2.0, the latest standard, defines high link speed, which is 3× faster than the recent embedded multimedia card (eMMC). In this context, we develop a UFS 2.0 device that introduces new features to the conventional embedded NAND storage device controller architecture to improve read performance. Figure 19.3.2 shows a block diagram of our controller. We improve the read performance in the following ways: 1) suppress the number of NAND read accesses and reduce the read latency by introducing unified memory (UM) and caching data for address translations on it, 2) increase the number of NAND chips activated simultaneously with dedicated hardware and new command scheduling, and 3) maximize bandwidth by supporting 5.8Gb/s 2-lane M-PHY link with low-power analog circuits.