Kenji Nishida

A priority forwarding scheme for real-time multistage interconnection networks

The authors propose a priority control scheme for packet switching multistage networks, called priority forwarding, which prevents priority inversion, a situation in which higher priority packets are blocked by lower priority packets. In an N*N omega network, the worst case delay of the priority forwarding scheme on the highest priority packet is O(log/sup 2/ N), while that for round-robin arbitration is O(N). Simulation results show that the priority forwarding scheme offers shorter delays for higher priority packets without throughput degradation and fits least-laxity-first control. The hardware implementation cost of this scheme is relatively small and requires no extra signal lines between routers. Consequently, this scheme offered predictability, scalability, and implementation eligibility.<<ETX>>

Real-time parallel architecture for sensor fusion

Abstract Sensor fusion is an example of an intelligent system which must simultaneously process a large amount of sensor data and perform intelligent computations. To satisfy the enormous computational requirements of such a system, we believe it must be implemented on a parallel architecture with special support for real-time computation. This paper describes a real-time parallel architecture that can handle sensor fusion processing by using processors tightly coupled with a priority handling network. The processor has a priority queue, which sends the two highest priority processes to the execution part of the processor. The processor has two pipelines: one is dedicated to the execution of the highest priority process, and the other is used to handle inserted instructions and to dynamically process administration during execution of the next highest priority process. Synchronization can be implemented with register read and write operations, which effectively provide very high speed fine-grain synchronization. When a currently executing thread must wait for a synchronization, the processor can switch contexts quickly by using hardware-supported multiple context register sets. The network is a prioritized multi-stage network which avoids the priority inversion problem, giving predictable process execution times to the system, and enabling its use for intelligent, real-time applications.

CODA-R: a reconfigurable testbed for real-time parallel computation

Recently the emergence of reconfigurable Field Programmable Gate Arrays (FPGAs) has given rise to a new form of computing engine using a dynamically changing architecture of processing elements. One major benefit of using FPGAs is that different architectural variations can easily be tested and evaluated on real applications. The other benefit is that some functions can be compiled and directly executed by hardware to shorten the total execution time. These benefits can also be applied to a real-time system. We have developed a prototype reconfigurable real-time parallel system CODA-R. Its key feature is that reconfigurable processing elements or units are connected by a priority-based real-time network. In this paper, we provide the technical justification for a reconfigurable real-time parallel architecture and the architecture of CODA-R and discuss them and also present some preliminary evaluation results.

Parallel multi-context architecture with high-speed synchronization mechanism

Current interest in parallel processing architecture is focused on compatibility of extracting parallelism and improving processor utilisation. The authors propose a new parallel processing architecture called CODA which can attain a high processor utilization while extracting parallelism effectively. CODA is based on single-thread pipeline architecture with advanced instruction fetch, which uses processors efficiently. Synchronization can be performed implicitly at a register reading to provide high-speed fine-grain synchronization effectively. CODA also has a hardware multi-context support which reduces the cost of context switch caused by synchronization. Synchronization and packet communication ability are effectively integrated into an execution pipeline by an instruction insertion mechanism.<<ETX>>

Performance comparison of real-time architectures using simulation

This paper presents a performance comparison of real-time system architectures. A discrete event-driven, task-based simulator is developed for evaluating the performance of parallel and distributed real-time systems. Real-time system components such as processor, network architectures, and scheduling policy are included in the simulator. Simulation results show that priority-based communication and scheduling are more suitable for real-time systems than FIFO-based. The strategy of having a dedicated processor, which produces no effect on task execution by scheduling and packet/interrupt handling, is proven to enhance schedulability and predictability. This paper suggests a method for finding an appropriate real-time architecture for users having real-time requirements through the performance prediction of real-time systems.