Kenneth M. Mackenzie

Software caching using dynamic binary rewriting for embedded devices

A software cache implements instruction and data caching entirely in software. Dynamic binary rewriting offers a means to specialize the software cache miss checks at cache miss time. We describe a software cache system implemented using dynamic binary rewriting and observe that the combination is particularly appropriate for the scenario of a simple embedded system connected to a more powerful server over a network. As two examples, consider a network of sensors with local processing or cell phones connected to cell towers. We describe two software cache systems for instruction caching only using dynamic binary rewriting and present results for the performance of instruction caching in these systems. We measure time overheads of 19% compared to no caching. We also show that we can guarantee a 100% hit rate for codes that fit in the cache. For comparison, we estimate that a comparable hardware cache would have space overhead of 12-18% for its tag array and would offer no hit rate guarantee.

Stampede: a cluster programming middleware for interactive stream-oriented applications

Emerging application domains such as interactive vision, animation, and multimedia collaboration display dynamic scalable parallelism and high-computational requirements, making them good candidates for executing on parallel architectures such as SMPs and clusters of SMPs. Stampede is a programming system that has many of the needed functionalities such as high-level data sharing, dynamic cluster-wide threads and their synchronization, support for task and data parallelism, handling of time-sequenced data items, and automatic buffer management. We present an overview of Stampede, the primary data abstractions, the algorithmic basis of garbage collection, and the issues in implementing these abstractions on a cluster of SMPs. We also present a set of micromeasurements along with two multimedia applications implemented on top of Stampede, through which we demonstrate the low overhead of this runtime and that it is suitable for the streaming multimedia applications.

Energy-efficient network memory for ubiquitous devices

Energy and delay tradeoffs occur when a design moves some or all local storage out of the embedded device and into a remote server. Using the network to access remote storage in lieu of local memory can result in significant power savings.

Performance study of a cluster runtime system for dynamic interactive stream-oriented applications

Emerging application domains such as interactive vision, animation, and multimedia collaboration need specialized runtime systems that provide support mechanisms to enable plumbing, cross module data transfer, buffer management, synchronization and so on. Using Stampede, a cluster programming system that is designed to meet the requirements of such applications, we quantify the performance of such mechanisms. We have developed a timing infrastructure that helps tease out the time spent by an application in different layers of software, viz., the main algorithmic component, the support mechanisms, and the raw messaging. Several interesting insights have surfaced from this study. First, memory allocation does not take up a significant amount of the execution time despite the interactive and dynamic nature of the application domain. Second, the Stampede runtime adds a minimal overhead over raw messaging for structuring such applications. Third, the results suggest that the thread scheduler on Linux may be more responsive than the one on Solaris. Fourth, the messaging layer spends quite a bit of time in synchronization operations. Perhaps the most interesting result of this study is that general-purpose operating systems such as Linux and Solaris are quite adequate to meet the requirements of emerging dynamic interactive stream-oriented applications.

Rapid Synthesis of Pattern Classification Circuits

We describe digital circuit synthesis and placement algorithms specialized for the domain of pattern matching circuits implemented in reconfigurable logic. We propose to use these algorithms as part of a system for implementing high-throughput pattern classification, for instance as part of a packet filter in a internetwork router. The goals of the approach are throughputs on the order of 100M classifications per second with reconfiguration times (including all synthesis) on the order of 10 seconds. We evaluate the algorithms using rulesets from two pattern classification problems in networking: IP routing (41,000 rules on 32 bits) and IP firewalling (180 rules on 100 bits) and compare their performance against standard tools. We find that the fast synthesis tools suffer about a 2× increase in circuit size but achieve substantial speedups over standard tools.