Kenneth P. Parker

Test coverage: what does it mean when a board test passes?

Characterizing board test coverage as a percentage of devices or nodes having tests does not accurately portray coverage, especially in a limited access testing environment that today includes a variety of diverse testing approaches from visual and penetrative inspection to classical in-circuit test. A better depiction of test coverage is achieved by developing a list of potential defects referred to as the defect universe, where the capabilities of the chosen test strategy are not considered in development of this defect list. Coverage is measured by grading the capabilities of each test process against the defect universe. The defect universe is defined to be meaningful to the bulk of the electronics industry and to provide a consistent framework for coverage metrics and comparisons.

A new probing technique for high-speed/high-density printed circuit boards

Bullock in 1987 [Bull87] provided design-for-test (DFT) rules for probing printed circuit boards for in-circuit testing. Many of these rules stand in good stead even today. However, recent technical advances in operational board speed are leading some to believe that in-circuit testing cannot be performed on the high-speed sectors of boards soon to be designed. Due to the increasing usage of high-speed circuitry, there is worry in our industry that in-circuit testing is marginalized with no good substitute available. It is the purpose of This work to show how access can be maintained, even on highly dense gigabit logic boards.

The effects of defects on high-speed boards

Printed circuit boards are steadily becoming faster. They have higher clock speeds, and edge rates on data signals have dropped down into the 100s of picoseconds. This presents some new challenges to the board test world because certain defects we did not do a good job covering in the past can no longer be ignored

Testing bridges to nowhere - combining Boundary Scan and capacitive sensing

As printed circuit board dimensions continue to decrease, in-circuit tester (ICT) access using a bed-of-nails plus capacitive sensing is increasingly difficult. Stimulus injection using IEEE 1149.1 Boundary-Scan has been proposed as an alternative, but without modification it has significant limitations. An IEEE-supported Working Group is developing an extension entitled, “1149.8.1 - Draft Standard for Boundary-Scan-Based Stimulus of Interconnects to Passive and/or Active Components”. It would add capabilities to 1149.1 that facilitate testing of connections to non-Boundary-Scan components, especially passive components and vacant connectors that are connected to devices equipped with 1149.8.1 facilities. This paper describes existing limitations, IC design changes that would address them, some experimental results, and a summary of how this proposed standard is evolving.

Frequency detection-based boundary-scan testing of AC coupled nets

The use of AC coupling capacitors on high-speed interconnects prevents the use of traditional DC-based boundary-scan techniques to test for board manufacturing defects. A solution is provided by a novel scheme that makes use of frequency discrimination using simple digital circuits that are easily integrated with the 1149.1 boundary-scan standard. Simulation results are presented which show the effectiveness of this method, and its robustness and scalability are compared with alternative solutions.

Bead probes in practice

Bead probes, a technology for in-circuit test probing of high-speed and/or high-density printed circuit boards was introduced at the 2004 International Test Conference as stated in K. P. Parker (2004). Since then much experimentation has been done with bead probe technology, and a large, high-density board has been designed and produced that makes use of them. This paper discusses the learning from these efforts

IEEE P1149.6: a boundary-scan standard for advanced digital networks

Very high-speed, digital technology is imposing new requirements on test logic that will limit the effectiveness of current IEEE 1149.1 based testing. IEEE P1149.6 is an extension to IEEE 1149.1 that attempts to standardize the boundary-scan structures and methods required to ensure simple, robust and minimally intrusive boundary-scan testing of advanced digital networks which are not adequately addressed by existing standards. This includes AC-coupled networks, differential networks or both. This paper will describe the work that has been done thus far by the P1149.6 working group including: defects to be targeted by the proposed standard, physical layer implementation for both the driver and receiver, verification of proposed solutions through SPICE modeling, BSDL and tools implications. The paper will also discuss some of the challenges faced by the working group and will discuss new approaches taken on by the working group in the development of the proposed standard.

An outlier detection based approach for PCB testing

Capacitive Leadframe testing is an effective approach for detecting faults in printed circuit boards. Capacitance measurements, however, are affected by mechanical variations during testing and by tolerances of electrical parameters of components, making it difficult to use threshold based techniques for defect detection. A novel approach is presented for identifying boards that are likely to be outliers. Based on Principal Components Analysis (PCA), this approach treats the set of capacitance measurements of individual connectors or sockets in a holistic manner to overcome the measurement and component parameter variations inherent in test data. The effectiveness of the method is evaluated using measurements on three different boards. Enhancements to the technique to increase the resolution of the method are presented and evaluated.

Augmenting Boundary-Scan Tests for Enhanced Defect Coverage

Strict analyses of boundary-scan test coverage performed on real-world printed circuit board topologies reveal significant holes in test coverage. Rather than abandon boundary-scan, it is preferable to augment boundary-scan test with other technologies that improve the overall ability to detect defects.

Finding power/ground defects on connectors — a new approach

Printed circuit boards are steadily becoming faster, and as a result, relatively ordinary defects in connectors and sockets can now have more subtle and damaging effects. At the same time these defects defy detection by conventional technologies. This paper surveys existing tests for these defects and introduces a new solution based on network parameter measurements.