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Kenneth T. Chin

Hewlett-Packard

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Publication

Featured researches published by Kenneth T. Chin.

Archive | 2001

Computer system with adaptive memory arbitration scheme

Kenneth T. Chin; Jerome J. Johnson; Phillip M. Jones; Robert A. Lester; Gary J. Piccirillo; Jeffrey C. Stevens; Michael J. Collins; C. Kevin Coffee

Archive | 1998

System and method for aligning an initial cache line of data read from local memory by an input/output device

Kenneth T. Chin; Clarence K. Coffee; Michael J. Collins; Jerome J. Johnson; Phillip M. Jones; Robert A. Lester; Gary J. Piccirillo

Archive | 1997

Accelerated Graphics Port two level Gart cache having distributed first level caches

Phillip M. Jones; Robert Allan Lester; Kenneth T. Chin

Archive | 2001

System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom

Kenneth T. Chin; Clarence K. Coffee; Michael J. Collins; Jerome J. Johnson; Phillip M. Jones; Robert A. Lester; Gary J. Piccirillo

Archive | 1998

Computer system employing memory controller and bridge interface permitting concurrent operation

Kenneth T. Chin; Jerome J. Johnson; Phillip M. Jones; Robert A. Lester; Gary J. Piccirillo; Jeffrey C. Stevens; C. Kevin Coffee; Michael J. Collins; John E. Larson

Archive | 2001

Next snoop predictor in a host controller

Phillip M. Jones; Paul B. Rawlins; Kenneth T. Chin

Archive | 1998

System and method for improving processor read latency in a system employing error checking and correction

Kenneth T. Chin; Clarence K. Coffee; Michael J. Collins; Jerome J. Johnson; Phillip M. Jones; Robert Allen Lester; Gary J. Piccirillo

Archive | 1998

Computer system with improved memory access

Kenneth T. Chin; Jerome J. Johnson; Phillip M. Jones; Robert A. Lester; Gary J. Piccirillo; C. Kevin Coffee; Michael J. Collins

Archive | 1998

System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache

Kenneth T. Chin; Michael J. Collins; John E. Larson; Robert A. Lester

Archive | 1998

System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter

Kenneth T. Chin; Clarence K. Coffee; Michael J. Collins; Jerome J. Johnson; Phillip M. Jones; Robert A. Lester; Gary J. Piccirillo

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Collaboration

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Phillip M. Jones

Hewlett-Packard

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Robert A. Lester

Hewlett-Packard

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Gary J. Piccirillo

Hewlett-Packard

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Jerome J. Johnson

Hewlett-Packard

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David L. Matthews

Hewlett-Packard

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Dwight D. Riley

Hewlett-Packard

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Hahn Vo Norden

Hewlett-Packard

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Hubert E. Brinkmann

Hewlett-Packard

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James Xuan Dinh

Hewlett-Packard

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John E. Larson

Hewlett-Packard

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