Keon-Jik Lee

Linear systolic multiplier/squarer for fast exponentiation

This paper presents a new linear systolic multiplier/squarer that can compute modular multiplication and squaring simultaneously by extracting the common computable parts using a right-to-left exponentiation. The proposed method is able to reduce the latency by 49 and 32% in the worst and average case, respectively, when compared to the method that computes modular multiplication and squaring in sequence. The new systolic multiplier/squarer is highly regular, nearest-neighbor connected, and thus well suited for VLSI implementation.

Low complexity semi–systolic multiplication architecture over GF(2m)

This paper presents a semi-systolic Montgomery multiplier based on the redundant basis representation of the finite field elements. The proposed multiplier has less hardware and time complexities compared to related multipliers. We also propose a serial systolic Montgomery multiplier that can be applied well in space-limited hardware. Furthermore, a simple inversion based on the proposed scheme is presented.

Design of a linear systolic array for computing modular multiplication and squaring in GF(2m)

Abstract One of the main operations for the public key cryptosystem is the modular exponentiation. In this paper, we analyze the Montgomerys algorithm and design a linear systolic array for performing both modular multiplication and modular squaring simultaneously. The proposed systolic array with less hardware complexity can be designed by making use of common-multiplicand multiplication in the right-to-left modular exponentiation over GF(2 m ). For the fast computation of the modular exponentiation, the proposed systolic array has 1.25 times improvement in area-time complexity when compared to existing multipliers. The proposed systolic array suffers a little loss in time complexity, but it has 1.44 times improvement in area complexity since it executes the common parts that exist in the simultaneous computation of both modular multiplication and squaring only once. It could be designed on VLSI hardware and used in IC cards.

Efficient systolic modular multiplier/squarer for fast exponentiation over GF (2 m )

Using the concept of common components, this letter shows that field multiplication and squaring over GF(2m) can be efficiently combined, with little hardware overhead. The analysis results show that about 39.23% area-time (AT) complexity is improved when we employ the combined systolic multiplier/squarer instead of implementing the multiplier and the squarer separately in the least significant bit (LSB)-first exponentiation. The proposed architecture features regularity, unidirectional data flow, and local interconnection, and thus is well suited to VLSI implementation.

Enhancement of a modified radix-2 Montgomery modular multiplication

Recently, Manochehri et al. proposed a modified radix-2 Montgomery modular multiplication with a new recording method. In this letter, we present an improvement to their scheme that makes it simpler and faster. Manochehri et al.’s algorithm requires n + 2 iterations, whereas the proposed (non-pipelined) algorithm requires n + 2 iterations. Moreover, there is no need for post-processing to obtain the correct output, nor for a non-standard operation such as bitwise subtraction. The area/time complexity of our pipelined multiplier is reduced by approximately 24.36% compared to Manochehri et al.’s multiplier. The proposed architecture is simple, modular, and regular. Moreover, it exhibits low complexity and propagation delay. Accordingly, it is well suited for VLSI implementation.

Digit-serial-in-serial-out systolic multiplier for Montgomery algorithm

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Partitioned systolic multiplier for GF(2/sup m/)

This paper presents a partitioned systolic array with an arbitrary number of PEs for MSB-first approach multiplication in GF(2/sup m/) based on the polynomial representation. As compared to the related multipliers presented by Wang et al. the proposed partitioned systolic array requires significantly small number of basic cells. It requires only m/2 number of basic cells and has the same throughput rate as when it has 2 bands. The proposed systolic array architecture has an arbitrary number of PEs using the partitioning concept although it suffers a little loss of computation times.

New Digit-Serial Systolic Arrays for Power-Sum and Division Operation in GF(2 m ).

This paper implements a new digit-serial systolic array for the computation of a power-sum operation and a new digit-serial systolic divider using the proposed systolic power-sum array in GF(2 m ) with the standard basis representation. Both of the architectures possess features of regularity, modularity, and unidirectional data flow. As a consequence, they have low AT complexity and are well suited to VLSI implementation with fault-tolerant design. Furthermore, the proposed power-sum array is also possible to select the digit-size of the regular square form.

A new digit-serial systolic multiplier for finite fields GF(2/sup m/)

This paper presents a new digit-serial systolic multiplier for finite fields GF(2/sup m/). The hardware requirements of the proposed multiplier are less than those of the existing multiplier of the same class, while maintaining the same cell delay. The proposed multiplier possesses the features of regularity, modularity, and unidirectional data flow. Thus, it is well suited to VLSI implementation. If the proposed digit-serial multiplier chooses the digit size L appropriately, it can meet the throughput requirement of a certain application with minimum hardware.

Reduced complexity polynomial multiplier architecture for finite fields GF (2 m )

This letter presents a low-complexity semi-systolic array implementation for polynomial multiplication over GF(2m). We consider finite field Montgomery modular multiplication (MMM) based on two-level parallel computing approach to reduce the cell delay, latency, and area-time (AT) complexity. Compared to related multipliers, the proposed scheme yields significantly lower AT complexity.