Ketan R. Shah

Ball grid array solder joint failure envelope development for dynamic loading

Solder joint interfaces with motherboard (MB) and/or substrate in ball grid array (BGA) packages have been observed to crack and create electrical opens during shock and drop dynamic testing. An experimental and numerical methodology that defines a failure envelope for a given package technology, and ensures the envelope is applicable for dynamic loading at MB and system-level testing, is developed. The quantitative magnitude of the envelope is defined by performing testing on a coupon board with the BGA package and correlating the coupon-level numerical model with the test data. The validity of the approach is shown by simulating a MB-level model with a surface mount BGA package and identifying sensitivity of the force state to the boundary conditions of mass and MB stiffness attributes. A MB that is pre-stressed due to assembly deflections in a system (slow loading) is subjected to shock test (fast loading) is an example when two extreme load rates are combined together. The validity of the approach based on solder material creep and plasticity is shown and is verified by testing with mixed rate loading.

Ultrabook™: Doing more with less

Mobile Original Equipment Manufacturers (OEMs) place great emphasis on creating unique system designs to differentiate themselves in the mobile market. Intel Corporations introduction of the Intel Ultrabook™ segment and low power processors provides a path for innovation and thinking “outside the box” of the traditional notebook PC. This paper will highlight 3 innovative examples of doing more with less with Configurable TDP, Configurable Tj, and Fan Speed Optimization for battery life.