Keun-Sup Lee

Software optimization of the MPEG-audio decoder using a 32-bit MCU RISC processor

This paper proposes optimization techniques to implement MPEG audio decoding algorithms in real-time using a general-purpose 32-bit MCU RISC processor. We implemented an MP3/AAC decoder using an ARM-based RISC MPU and its test board. Both the designed decoders with the proposed optimizations could achieve decoding processes in real-time within an operating frequency of 35 MHz.

An architecture and implementation of MPEG audio layer III decoder using dual-core DSP

A new architecture for the MP3 decoding system is proposed and implemented. The proposed system is based on a processor employing a dual-core (DSP and RISC) architecture. The MP3 decoding algorithm is implemented using the DSP core with high accuracy, and the RISC core performs bitstream buffering and system control in conjunction with a user interface. The system with this configuration can support an efficient parallel processing between DSP and RISC cores, so that it is possible to minimize the computational overhead. The implemented system employs a flash memory card for the storage, and it has a file management system that is compatible with PC. Also, it supports all sampling rates and data rates specified in MPEG-1/2 standards. The MP3 decoder developed is suitable for portable communication devices such as cellular telephones since it features high audio quality, low-power consumption and cost effectiveness.

High quality MPEG-audio layer III algorithm for a 16-bit DSP

This paper presents a high quality MPEG-1/2 layer-III decoding algorithm, which is optimized for a 16-bit fixed-point arithmetic. Motorola DSP56600 16-bit DSP family processor is chosen as a target processor, and quantization noise due to fixed-point arithmetic is minimized for each decoding routine via C language-based fixed-point simulations. To maintain high audio quality with limited data precision, finite word length effects of each routine are evaluated. Also, double-precision arithmetic is tried for each routine and their effects are analyzed. Furthermore, to compromise the audio quality with the system complexity, the evaluation is extended to several fast algorithms for IMDCT and sub-band synthesis. To measure the quality of decoded output, ISO/IEC 13818-4 compliance test sequence is applied to the proposed algorithm. This test showed that the proposed decoding algorithms ensured full compliance with ISO/IEC 13818-3 audio decoder.

A VLSI implementation of MPEG-2 AAC decoder system

This paper presents a real-time MPEG-2 AAC decoding system, which can decode 2-channel main profile MPEG-2 AAC bitstream. The system consists of a simple fixed-point programmable DSP core and two hardwired logic modules, which perform Huffman decoding and prediction respectively. To verify the designed decoding system, simulator model has been developed based on C-language. For the verification of decoding algorithm, the 16-bit PCM output of the system was compared with the result of the floating-point simulation, and the result showed the maximum of 2-bit difference. For the verification of real-time decoding, the number of the clock cycles in the worst simulation case was compared with that of the required clock cycles for the real-time decoding, and the result verified the real-time decoding of designed system.