Kevin Chiang

Electrical characterization and structure investigation of quad flat non-lead package for RFIC applications

The quad flat non-lead (QFN) package is a both chip scale package and plastic encapsulated package with a copper leadframe substrate. The purpose of this paper was to establish the wideband equivalent circuit model of QFN packages for RF applications. Only short-path configuration was required for S-parameter measurement to achieve this purpose. Comparison of S11 and S21 between S-parameter measurement and optimized equivalent circuit model verified that those results were well matched and optimized. The parasitic parameters of the equivalent circuit were reliable up to 6 GHz. The methods proposed in this paper reduce the costs for samples preparation and chip simulation run time. In order to realize the package performance for higher frequency applications further, a 3D structure electromagnetic field simulator, HFSS, was used to simulate from 0.1 to 20 GHz for five modified package structures. Simulation results indicated that the QFN32 package that utilized the double bonding wires with a lower dielectric-constant molding compound and larger die-pad is the best structure for RF applications.

Comparative Analysis of Electrical Performance on Coreless and Standard Flip-Chip Substrate

In recent years, more and more devices are designed by high-performance flip-chip ball grid array (FCBGA) packages due to the requirement on large number of I/O pads, small pitch, and high operation frequency of ASIC. Many studies were done on FCBGA packages. Some of these works were focused on thinner structures. In the study of this paper, our targets will be focused on the coreless and standard FCBGA cases. By directly replacing the BT-core of the standard substrate with a thinner build-up dielectric layer, the coreless design is a good choice to decrease the cost. This replacement makes some differences between the standard thick BT-core and the new thinner build-up substrates. Our study analyzes the electrical performance caused by these differences. With the simulation approach, the analyses include the power integrity (PI) and signal integrity (SI) issues in frequency and time domains on both coreless and standard substrates. In the final results, we found that the coreless substrates could get a better electrical performance, for examples, the smaller coupling between the signal nets, the lower impedance of the power delivery system. The results from these analyses could give a useful reference for chip designers while they make a decision on package.

Electrical characterization of quad flat non-lead package for RFIC applications

The QFN package is a near chip scale package plastic encapsulated package with a coppery leadframe substrate. The purpose of this paper was to establish the wideband equivalent circuit model of QFN packages for RF applications. Only short-path configuration was required for S-parameter measurement to achieve this purpose. The comparison of S11 and S21 between S-parameter measurement and optimized equivalent circuit model verified that those results were well matched and optimized. The parasitic parameters of equivalent circuit were reliable up to 6 GHz. The methods proposed in this paper may reduce the cost for samples preparation and chip simulation run time.

Electrical analyses of TSV-RDL-bump of interposers for high-speed 3D IC integration

As the progress of the packaging technology for the electronic consuming devices, the customer demands more and more. From the trend of the development on electronic devices, it shows that these demands require for more functions or higher density of devices within a limited space. By the capabilities of the 3D-IC technology, it could support such a design with multi-purposes including a smaller size, the high-speed and multi-functions. There are many approaches and technologies to make the 3D-IC. Amount of them, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path of the circuit in a device. And hence, this device may support a faster operation. In this study, we analyze the different designs based on two TSV technologies, the Cu-filled and coaxial-type TSVs. By using the simulation approach, we evaluate the performances of these proposed designs. And, the results in our study should have the benefits for designing the interposer substrates which are used for developing the 3D-IC.

Electrical characterization of through silicon via (TSV) for high-speed memory application

In this paper, we study three types of the interconnection between die and die for system-in-package (SIP). The first is the two-dimensional system-in-package (2-D SIP) which is side-by-side dies with wire bonding interconnection. The second is the three-dimensional system-in-package (3-D SIP) which stacks up two dies with wire bonding interconnection and the third is 3-D SIP with TSV interconnection. The propagation delay, insertion loss and return loss results will be compared among these three types interconnection. TSV interconnection shows the best performance among the three types due to its shortest interconnection path between die to die. We also study electrical characteristics of different TSV structure, like TSV size, TSV height, TSV pitch and the number of TSV stacked. Based on the analysis results, we will provide the design guideline for designer reference.

High-speed electrical design study for 3D-IC packaging technology

As the advance of the packaging technology for the electrical consuming demands, it requires for more functions or increasing the density of devices within a smaller space. By the capabilities of the 3D-IC technology, it could support a design included smaller size, high-speed and multi-functions. One of the 3D-IC techs, the stacking with Through-Silicon-Via (TSV), plays a very important role. It shortens the path, and hence, increases the bandwidth of the device. In this study, we evaluate the TSV effects in usual high-speed electrical designs. There are two issues, the impedance-control and isolation. By using the EM simulation solver, we estimate the performances of different designed models about these two issues. And, this result should have the benefits for the development on the designs in the interposer substrates used for 3D-IC technology.

DDRII Memory Packages Electrical Performance Comparison of COSBGA, TFBGA, and Standard TSOPII

The memory storage technology revolution has taken the consumer electronics by a storm in just two years. The volatile memory Dynamic Random Access Memory (DRAM) for PC and notebook computing and gaming are increasing in density and speed. With all these improvement, the memory device packaging technology is also evolving rapidly, from the leadframe packages to BGA packages [2]. Under high frequency operation, the parasitics associated with package will significantly degrade the package performance. The DRAM packages are used primarily in the fabrication of DIMM modules that are inserted to the motherboards in PC and notebook computers. With newer DRAM technology in double date rate (DDR) and its second generation, DDR2, to be deployed just two years, it has higher clock rate and I/O number. Packages therefore are changing form the leadframe TSOP type 2 to faster CSPs such as fine pitch BGA (FBGA) and chip on substrate BGA (COSBGA). This paper is focused the COSBGA package [3,4]. In this paper, the packages electrical model have been established and performs signal integrity (SI) simulation. The COSBGA has smallest parasitics when comparison with other two packages. This paper also compares the performance of the COSBGA, TFBGA and TSOPII from crosstalk noise, time skew, insertion loss and return loss for IC designer reference.Copyright

RFICs packages electrical performance comparison of both ULTRA-CSP and Standard TSOP

The requirement for low cost, small size and high density for high-speed system drives the design of packages to smaller package size. ULTRA CSP is an advanced technology to meet the above targets. ULTRA CSP is a wafer level package developed by FCT. Under high frequency operation, the parasitics associated with the package will significantly degrade the package performance. An unsuitable package may cause resonance, coupling, impedance mismatch and frequency dependent loss. So, providing accurate package parasitics is critical to the success of the system design. In this paper, the electrical model of ULTRA CSP has been established based on the S-parameter simulation. When compared with the TSOP package, ULTRA-CSP shows smaller parasitics in the equivalent model. This paper also compares the performance of the ULTRA-CSP and Standard TSOP from the view point of propagation delay, crosstalk noise, insertion loss, return loss and maximum allowable working frequency. Based on the analysis result, is provided the package layout guideline for designer reference.

A novel decoupling capacitor for power integrity application in high-speed 3D-IC package system

In todays industries, utilizing the SMT capacitor is a mature technology and widely used. But, in the future, the 3D-IC stacking assembly, the SMT capacitor might not suitable for the application in the high-speed and higher frequency range. It is caused by the higher density power assumption in stacked 3D-IC configuration. In this study, we test the PDN performance with two conditions, including a practical surface-mounted capacitor model and a 3D Through-Silicon Interposer (TSI) capacitor model. Generally, a suitable SMT capacitor could be found by simulation tool to improve the impedance of a Power Delivery Network system. However, in this study, we also found out that a TSI capacitor could achieve better performance in higher frequency range.

EMI improvement study on advanced package design

At the present time, the package design faces demands, including the high-speed switching, low-voltage bias and minimization. The high-speed signals may induce not only signal integrity and power integrity issues, but also cause radiation and electromagnetic interference (EMI) problems. To evaluate a package design, near-field scan is a useful technique to investigate the radiation behavior. Our study is based on this near-field approach to estimate the radiation of a package by using a simulation tool. Several factors were investigated in this study. From the near-field results, we could conclude some useful concepts for package layout design.