Kevin R. Covi
IBM
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Publication
Featured researches published by Kevin R. Covi.
Ibm Journal of Research and Development | 2012
Thomas Strach; Frank E. Bosco; Kenneth L. Christian; Kevin R. Covi; Martin Eckert; Gregory R. Edlund; Roland Frech; Hubert Harrer; Andreas Huber; Dierk Kaller; Martin Kindscher; A. Z. Muszynski; G. A. Peterson; Claudio Siviero; Jochen Supper; Otto Torreiter; Thomas-Michael Winkel
In this paper, we describe the first- and second-level system packaging structure of the IBM zEnterprise® 196 (z196) enterprise-class server. The design point required a more than 50% overall increase in system performance (in millions of instructions per second) in comparison to its predecessor. This resulted in a new system design that includes, among other things, increased input/output bandwidth, more processors with higher frequencies, and increased current demand of more than 2,000 A for the six processor chips and two cache chips per multichip module. To achieve these targets, we implemented several new packaging technologies. The z196 enterprise-class server uses a new differential memory interface between the processor chips and custom-designed server memory modules. The electrical power delivery system design follows a substantially new approach using Vicor Factor Power® blocks, which results in higher packaging integration density and minimized package electrical losses. The power noise decoupling strategy was changed because of the availability of deep-trench technology on the new processor chip generation.
Ibm Journal of Research and Development | 1992
Kevin R. Covi
In an Enterprise System/9000™ (ES/9000™) processor, a fault-tolerant power system composed of multiple power supplies connected in parallel provides thousands of amperes of current to low-voltage (1–2 V) logic circuit boards, monitors the voltage at each board, and immediately responds to compensate for failure of a supply. If a supply fails, the very fast closed-loop response redistributes the current uniformity among the remaining supplies and allows the normal functioning of the processor logic to continue uninterrupted. This rapid response is not obtained from a conventional two-loop (current-mode) feedback power supply because the loop bandwidth is restricted by a resonance that develops in the power distribution. A third feedback loop that is added to each supply controls this power distribution resonance and makes possible the wide loop bandwidth necessary to achieve the required power system control. Analysis is presented of a three-loop control system, and a simulation of its application to a typical ES/9000 power system is described.
Archive | 1987
Robert Anthony Biamonte; Joseph William Bogdanski; Kevin R. Covi; Herman Paul Meyer; Daniel Ira Rafkind
Archive | 2002
Kevin R. Covi; Raymond A. Longhi; Edward J. Seminaro; Steven G. Shevach
Archive | 2001
Kevin R. Covi; Robert B. Schlak; Raymond J. Harrington; Edward J. Seminaro
Archive | 1992
Miguel A. Berrios; Kevin R. Covi
Archive | 1988
Robert Anthony Biamonte; Joseph William Bogdanski; Kevin R. Covi; Herman Paul Meyer; Daniel Ira Rafkind
Archive | 1990
Kevin R. Covi; William J. Petrowsky; James H. Spreen
Archive | 1992
Steven J. Ahladas; Kevin R. Covi
Archive | 1990
Kevin R. Covi; Donald Paul Rearick