Kevin Stanton
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Featured researches published by Kevin Stanton.
Proceedings of the IEEE | 2013
Michael Johas Teener; Andre N. Fredette; Christian Boiger; Philippe Klein; Craig Gunther; David Olsen; Kevin Stanton
The IEEE 802.1 Audio/Video Bridging Task Group has created a series of IEEE standards that specify methods used to provide the appropriate quality of service (QoS) for audio/video (A/V) streams in a heterogeneous network. This paper describes the requirements for such a network and summarizes the methods described in these standards and how they are used in some example higher layer protocols.
Technical Note (NIST TN) - 1867 | 2015
John C. Eidson; Charles Barry; David Broman; Leon Goldin; Bob Iannucci; Kevin Stanton
A new economy built on the massive growth of endpoints on the internet will require precise and verifiable timing in ways that current systems do not support. Applications, computers, and communica ...
international conference on hardware/software codesign and system synthesis | 2016
Aviral Shrivastava; Patricia Derler; Ya-Shian Li Baboudr; Kevin Stanton; Mohammad Khayatian; Hugo A. Andrade; John C. Eidson; Sundeep Chandhoke
Many modern cyber-physical systems (CPS), especially industrial automation systems, require the actions of multiple computational systems to be performed at much higher rates and more tightly synchronized than is possible with ad hoc designs. Time is the common entity that computing and physical systems in CPS share, and correct interfacing of that is essential to flawless functionality of a CPS. Fundamental research is needed on ways to synchronize clocks of computing systems to a high degree, and on design methods that enable building blocks of CPS to perform actions at specified times. To realize the potential of CPS in the coming decades, suitable ways to specify distributed CPS applications are needed, including their timing requirements, ways to specify the timing of the CPS components (e.g. sensors, actuators, computing platform), timing analysis to determine if the application design is possible using the components, confident top-down design methodologies that can ensure that the system meets its timing requirements, and ways and methodologies to test and verify that the system meets the timing requirements. Furthermore, strategies for securing timing need to be carefully considered at every CPS design stage and not simply added on. This paper exposes these challenges of CPS development, points out limitations of previous approaches, and provides some research directions towards solving these challenges.
international symposium on precision clock synchronization for measurement control and communication | 2015
John C. Eidson; Kevin Stanton
Distributed cyber-physical systems (CPS) are increasingly provided with an accurate and precise common sense of time using a variety of well established time distribution methods such as GNSS, IEEE 1588 and others. Less attention has been paid to the effective use of time in CPS and techniques and components to support such use. This paper reviews these topics and discusses critical components that are needed. If this infrastructure is properly realized recent work suggests that subject to well defined constraints, it will be possible to design CPS where timing is correct-by-construction.
reconfigurable computing and fpgas | 2015
Hugo A. Andrade; Patricia Derler; John C. Eidson; Ya Shian Li-Baboud; Aviral Shrivastava; Kevin Stanton
Timing and synchronization play a key role in cyber-physical systems (CPS). Precise timing, as often required in safety-critical CPS, depends on hardware support for enforcement of periodic measure, compute, and actuate cycles. For general CPS, designers use a combination of application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs) and conventional microprocessors. Microprocessors as well as commonly used computer languages and operating systems are essentially devoid of any explicit support for precise timing and synchronization. Modern computer science and microprocessor design has effectively removed time from the abstractions used by designers with the result that time is regarded as a performance metric rather than a correctness specification or criterion. There are interesting proposals and avenues of research to correct this situation, but the barrier is quite high for conducting proof of concept studies or collaborative research and development. This paper proposes a conceptual design and use model for a reconfigurable testbed designed specifically to support exploratory research, proof of concept, and collaborative work to introduce explicit support for time and synchronization in microprocessors, reconfigurable fabrics, language and design system architecture for time-sensitive CPS. Reconfigurable computing is used throughout the system in several roles: as part of the prototyping platform infrastructure, the measurement and control system, and the application system under test.
design automation conference | 2017
Aviral Shrivastava; Mohammadreza Mehrabian; Mohammad Khayatian; Patricia Derler; Hugo A. Andrade; Kevin Stanton; YaShian Li-Baboud; Edward Griffor; John C. Eidson
Time is a foundational aspect of Cyber-Physical Systems (CPS). Correct time and timing of system events are critical to optimized responsiveness to the environment, in terms of timeliness, accuracy, and precision in the knowledge, measurement, prediction, and control of CPS behavior. However, both the specification and verification of timing requirements of the CPS are typically done in an ad-hoc manner. While feasible, the system can become costly and difficult to analyze and maintain, and the process of implementing and verifying correct timing behavior can be error-prone. Towards the development of a verification testbed for testing timing behavior in tools and platforms with explicit time support, this paper first describes a way to express the various kinds of timing constraints in distributed CPS. Then, we outline the design and initial implementation of a distributed testbed to verify the timing of a distributed CPS analytically through a systematic framework. Finally, we illustrate the use of the verified timing testbed on two distributed CPS case studies.
ACM Transactions in Embedded Computing Systems | 2017
Mohammadreza Mehrabian; Mohammad Khayatian; Aviral Shrivastava; John C. Eidson; Patricia Derler; Hugo A. Andrade; Ya Shian Li-Baboud; Edward Griffor; Kevin Stanton
In order to test the performance and verify the correctness of Cyber-Physical Systems (CPS), the timing constraints on the system behavior must be met. Signal Temporal Logic (STL) can efficiently and succinctly capture the timing constraints of a given system model. However, many timing constraints on CPS are more naturally expressed in terms of events on signals. While it is possible to specify event-based timing constraints in STL, such statements can quickly become long and arcane in even simple systems. Timing constraints for CPS, which can be large and complex systems, are often associated with tolerances, the expression of which can make the timing constraints even more cumbersome using STL. This paper proposes a new logic, Timestamp Temporal Logic (TTL), to provide a definitional extension of STL that more intuitively expresses the timing constraints of distributed CPS. TTL also allows for a more natural expression of timing tolerances. Additionally, this paper outlines a methodology to automatically generate logic code and programs to monitor the expressed timing constraints. Since our TTL monitoring logic evaluates the timing constraints using only the timestamps of the required events on the signal, the TTL monitoring logic has significantly less memory footprint when compared to traditional STL monitoring logic, which stores the signal value at the required sampling frequency. The key contribution of this paper is a scalable approach for online monitoring of the timing constraints. We demonstrate the capabilities of TTL and our methodology for online monitoring of TTL constraints on two case studies: 1) Synchronization and phase control of two generators and, 2) Simultaneous image capture using distributed cameras for 3D image reconstruction.
MediaSync, Handbook on Multimedia Synchronization | 2018
Hugh Melvin; Jonathan Shannon; Kevin Stanton
In this chapter, we provide a comprehensive overview of timing. We describe the underlying concepts that comprise timing through examples and then present a range of mature, standardised and evolving techniques to improve the so-called time awareness across the full Information and Communications Technology (ICT) infrastructure over which multimedia applications operate. Although the media synchronisation community is already acutely aware of timing issues, this chapter offers some valuable insights through its holistic approach to timing.
Archive | 2005
Kevin Stanton
Archive | 1999
Kevin Stanton; Jens P. Tagore Brage