Khurram Waheed

A 24mm 2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS

The RF transceiver is built on the Digital RF Processor (DRP) technology. The ADPLL-based transmitter uses a polar architecture with all-digital PM-FM and AM paths. The receiver uses a discrete-time architecture in which the RF signal is directly sampled and processed using analog and DSP techniques. A 26 MHz digitally controlled crystal oscillator (DCXO) generates frequency reference (FREF) and has a means of high-frequency dithering to minimize the effects of coupling from digitally controlled PA driver (DPA) to DCXO by de-sensitizing its slicing buffer.

Blind information-theoretic multiuser detection algorithms for DS-CDMA and WCDMA downlink systems

Code division multiple access (CDMA) is based on the spread-spectrum technology and is a dominant air interface for 2.5G, 3G, and future wireless networks. For the CDMA downlink, the transmitted CDMA signals from the base station (BS) propagate through a noisy multipath fading communication channel before arriving at the receiver of the user equipment/mobile station (UE/MS). Classical CDMA single-user detection (SUD) algorithms implemented in the UE/MS receiver do not provide the required performance for modern high data-rate applications. In contrast, multi-user detection (MUD) approaches require a lot of a priori information not available to the UE/MS. In this paper, three promising adaptive Riemannian contra-variant (or natural) gradient based user detection approaches, capable of handling the highly dynamic wireless environments, are proposed. The first approach, blind multiuser detection (BMUD), is the process of simultaneously estimating multiple symbol sequences associated with all the users in the downlink of a CDMA communication system using only the received wireless data and without any knowledge of the user spreading codes. This approach is applicable to CDMA systems with relatively short spreading codes but becomes impractical for systems using long spreading codes. We also propose two other adaptive approaches, namely, RAKE-blind source recovery (RAKE-BSR) and RAKE-principal component analysis (RAKE-PCA) that fuse an adaptive stage into a standard RAKE receiver. This adaptation results in robust user detection algorithms with performance exceeding the linear minimum mean squared error (LMMSE) detectors for both Direct Sequence CDMA (DS-CDMA) and wide-band CDMA (WCDMA) systems under conditions of congestion, imprecise channel estimation and unmodeled multiple access interference (MAI).

A 0.8mm 2 all-digital SAW-less polar transmitter in 65nm EDGE SoC

EDGE is currently the most widely used standard for data communications in mobile phones. Its proliferation has led to a need for low-cost 2.5G mobile solutions. The implementation of RF circuits in nanoscale digital CMOS with no or minimal process enhancements is one of the key obstacles limiting the complete SoC integration of cellular radio functionality with digital baseband. The key challenges for such RF integration include non-linearity of devices and circuits, device mismatches, process parameter spread, and the increasing potential for self-interference that could be induced by one function in the SoC onto another.

A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter

A polar modulator for wireless RF transmitters nonlinearly transforms complex-valued Cartesian baseband modulating signal into amplitude and phase components of the polar coordinate representation before they are recombined in a power amplifier. The resulting explosion in the bandwidth requirements of the polar components can so far be only tolerated for narrowband transmitters, such as EDGE of the 2G cellular. To enable polar topology for wideband transmitters, we propose a technique that alters the signal trajectory such that it avoids crossing (and proximity) of the constellation origin. The resulting substantial decrease of the polar modulator bandwidth is traded off against slight increase of in-band modulation distortion and adjacent channel leakage. We illustrate effectiveness of this method using wideband CDMA (WCDMA) of the 3G cellular. The technique is first mathematically analyzed for various tradeoffs followed by high-level modeling and simulation results. Since the technique is fully contained in the digital domain, its performance effects on the entire RF transmitter can be accurately simulated. A digital architecture to implement the proposed technique is also presented.

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm2 and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.

Cyclic spectral analysis of power line noise in the 3–200 kHz band

Narrowband OFDM Power Line Communication (NB-OFDM PLC) systems are a key component of current and future smart grids. NB-OFDM PLC systems enable next-generation smart metering, distributed control, and monitoring applications over existing power delivery infrastructure. It has been shown that the performance of these systems is severely limited by impulsive, non-Gaussian additive noise. A substantial component of this noise has time-periodic statistics (i.e. it is cyclostationary) synchronous to the AC mains cycle. In this work, we analyze the cyclic structure of power line noise observed in a G3 PLC system operating in the CENELEC 3-148.5 kHz band. Our contributions include: (i) the characterization of noise measurements in several urban usage environments, (ii) the development of a cyclic bit loading method for G3, and (iii) the quantification of its throughput gains over measured noise. Through this analysis, we confirm strong cyclostationarity in power lines and identify several sources of the cyclic noise.

Noise Analysis of Time-to-Digital Converter in All-Digital PLLs

In an all-digital PLL architecture the conventional phase-frequency detector is replaced in part by a time-to-digital converter. This paper presents an exact analysis of the mechanism by which reference clock jitter and/or supply/substrate noise are converted into TDC noise that is injected into the ADPLL loop. The cases of white and sinusoidal noise are considered and the analytical results are compared with simulations

Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences

We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the feedback variable oscillator phase. In modern nanoscale technologies, TDC has a time quantization of 5 to 30 ps. This deadband can potentially result in spurious tones, whenever a near integer-N relationship arises between the oscillator frequency and the TDC sampling process. This work proposes injection of a spectrum-friendly short sequence dither into the reference clock signal to overcome the quantization introduced limit-cycles. This results in robust phase tracking performance and spurious-free operation of the ADPLL, which was verified in a 65-nm CMOS GSM/EDGE transmitter.

Quantization noise improvement of Time to Digital converter (TDC) for ADPLL

A number of communication applications are moving to digitally motivated architectures for their radio frequency module. This includes GSM-EDGE, WLAN, Bluetooth, GSM-GPRS, WiMAX. The All Digital PLL(ADPLL) forms the core of this architecture. The objective of the ADPLL is to generate a clean carrier frequency ƒc, based on a input reference frequency ƒref. As part of the phase error measurement of the PLL, a Time to Digital converter(TDC) is used to measure the delay between ƒref clock edge and carrier clocking edge. An inverter chain is used to measure this delay as a integer number of basic inverter delay. This measurement error is termed TDC quantization error and effects the phase noise present in the final carrier. Due to the coarse delay of the basic inverter available, TDC introduces large quantization noise at the output of the PLL. This is too high for systems operating at high carrier frequencies or systems which have a tight phase noise requirement. This paper presents techniques to improve TDC quantization noise.

Spur-free all-digital PLL in 65nm for mobile phones

After the first-ever all-digital PLL (ADPLL) [1] for Bluetooth radios has proven benefits of CMOS scaling and integration, demonstrators for more challenging wireless standards have emerged [2–6]. In the ADPLL, however, the digitally-controlled oscillator (DCO) and time-to-digital converter (TDC) quantize the time and frequency tuning functions, respectively, which can lead to spurious tones and phase noise increase. As such, finite TDC resolution can distort data modulation and spectral mask at near integer-N channels, while finite DCO step size can add far-out spurs and phase noise. Also, a major underreported issue is an injection pulling of the DCO due to harmonics of the digital activity at closely-spaced frequencies, which can also create spurs. This work addresses all these problems and demonstrates RF performance matching that of the best-in-class traditional approaches.