Ki-Il Kum

Simulation-based word-length optimization method for fixed-point digital signal processing systems

Word-length optimization and scaling software that utilizes the fixed-point simulation results using realistic input signal samples is developed for the application to general, including nonlinear and time-varying, signal processing systems. Word-length optimization is conducted to minimize the hardware implementation cost while satisfying a fixed-point performance measure. In order to minimize the computing time, signal grouping and efficient search methods are developed. The search algorithms first determine the minimum bound of the word-length for an individual group of signals and then try to find out the cost-optimal solution by using either exhaustive or heuristic methods.

Combined word-length optimization and high-level synthesis of digital signal processing systems

Conventional approaches for fixed-point implementation of digital signal processing algorithms require the scaling and word-length (WL) optimization at the algorithm level and the high-level synthesis for functional unit sharing at the architecture level. However, the algorithm-level WL optimization has a few limitations because it can neither utilize the functional unit sharing information for signal grouping nor estimate the hardware cost for each operation accurately. In this study, we develop a combined WL optimization and high-level synthesis algorithm not only to minimize the hardware implementation cost, but also to reduce the optimization time significantly. This software initially finds the WL sensitivity or minimum WL of each signal throughout fixed-point simulations of a signal flow graph, performs the WL conscious high-level synthesis where signals having the similar WL sensitivity are assigned to the same functional unit, and then conducts the final WL optimization by iteratively modifying the WLs of the synthesized hardware model. A list-scheduling-based and an integer linear-programming-based algorithms are developed for the WL conscious high-level synthesis. The hardware cost function to minimize is generated by using a synthesized hardware model. Since fixed-point simulation is used to measure the performance, this method can be applied to general, including nonlinear and time-varying, digital signal processing systems. A fourth-order infinite-impulse response filter, a fifth-order elliptic filter, and a 12th-order adaptive least mean square filter are implemented using this software.

AUTOSCALER for C: an optimizing floating-point to integer C program converter for fixed-point digital signal processors

A translator which converts C-based floating-point digital signal processing programs to optimized integer C versions is developed for convenient programming and efficient use of fixed-point digital signal processors (DSPs). It not only converts data types and supports automatic scaling, but also conducts shift optimization to enhance execution speed. Since the input and output of this translator are ANSI C compliant programs, it can be used for any fixed-point DSP that supports ANSI C compiler. The number of shift operations that are required for scaling in the converted integer programs is reduced by equalizing the integer word-lengths of relevant variables and constants. For an optimal reduction, a cost function that represents the overhead of scaling is formulated by considering the data- path of a target processor, program parsing, and profiling results. This cost function is then minimized by using either integer linear programming or simulated annealing algorithms. The translated integer C codes are 5-400 times faster than the floating-point versions when applied to TMS320C50, TMS320C60 and Motorola 56000 DSPs.

Word-length optimization for high-level synthesis of digital signal processing systems

Word-length optimization software is developed not only to reduce the hardware cost but also to minimize the optimization time. It inserts quantizers to a data flow graph representation, partitions the resultant graph, determines the minimum required word-length for each partitioned signal, conducts scheduling and binding using the minimum word-length information, and finally optimizes the word-lengths of functional units. Fixed-point simulation results are used as for the performance measure, thus this method can be applied to nonlinear and time-varying algorithms. Although this approach requires iterative fixed-point simulations, the search space is reduced significantly by grouping signals using the high-level synthesis, or hardware sharing, results. A fourth-order IIR filter, a fifth-order elliptic filter, and a 12th-order adaptive LMS filter are implemented using this software. The hardware cost of functional units is reduced by 25% in the IIR filter and 7% in the elliptic filter compared to the previous results.

Fixed-point optimization utility for C and C++ based digital signal processing programs

Two fixed-point optimization utility programs, the range estimator and the fixed-point simulator, are developed for scaling and wordlength determination of digital signal processing algorithms written in C or C++ language. By exploiting the operator overloading characteristics of C++ language, range estimation and fixed-point simulation can be conducted just by modifying the variable declaration of the original floating-point digital signal processing program. Since this utility evaluates the range and the fixed-point performance by simulation, not by analytical methods, it is easily applicable to nearly all type of digital signal processing algorithms including non-linear and time-varying systems. In addition, this utility software can be used for comparing the fixed-point characteristics of different implementation architectures.

A floating-point to integer C converter with shift reduction for fixed-point digital signal processors

A floating-point to integer C program translator is developed for convenient programming and efficient use of fixed-point programmable digital signal processors (DSPs). It not only converts data types and supports automatic scaling, but also conducts shift optimization to enhance execution speed. Since the input and output of this translator are ANSI C compliant programs, it can be used for any fixed-point DSP that supports ANSI C compiler. A shift reduction method is developed for minimizing the scaling overhead of translated integer C programs. It considers the data-path of a target processor and profiling results. Using the shift reduction method, 4% to 37% speedup is obtained. The translated integer C codes are 20 to 400 times faster than the floating-point versions when applied to TMS320C50, TMS320C60 and Motorola 56000 DSPs.

Word-length determination and scaling software for a signal flow block diagram

Software for word-length determination and scaling of a general signal flow block diagram is developed for aiding the development of fixed-point digital signal processing algorithms. A fixed-point performance measure, such as signal to quantization noise ratio, and a hardware cost model are used as constraints to the optimization. Simulation using a real input signal is conducted for the evaluation of fixed-point performance. The number of simulations required for the optimization process is greatly reduced by employing netlist preprocessing and efficient search methods.<<ETX>>

A 2 way VLIW processor architecture for embedded multimedia applications

As the complexity of multimedia applications increases, the need for efficient and compiler-friendly processor architectures also grows. In this paper, a new multimedia processor architecture is proposed. This processor has a 2-issue VLIW architecture with 64-bit SIMD arithmetic functional units to exploit the instruction-level and subword data parallelism found in multimedia applications. Moreover, densely encoded instructions supporting memory operands, DSP-like addressing modes, and SIMD capability boost the performance while keeping the code size and hardware cost small. To maximally utilize this architecture, a software environment including a code converter, a VLIW compiler system, and a compiled simulator has also been developed. The processor core has been synthesized for LSI logic 0.25 /spl mu/m library, which results in the total gate count of 102 K. In spite of the relatively smaller issue rate, the proposed processor shows a comparable or higher performance in terms of both the cycle count and the code size when compared to the 8-issue TMS320C62xx, for DSP benchmark kernels and an H.263 video encoder.

Multiprocessor scheduling of a signal flow graph for workstation clusters

A multiprocessor code generator for workstation clusters is developed to prototype DSP (digital signal processing) algorithms represented by hierarchical signal flow graphs quickly. In order to reduce the communication overhead and utilize fairly large memory space in each workstation, the parallel block processing method which assigns one block of data to each processor in rotation is used. Firstly, a signal flow graph is scheduled in a higher hierarchy level with coarse grain partitioning. If the desired performance is not obtained, a finer grain scheduling is performed in the lower hierarchy. An MPEG2 audio encoder program is implemented in real time for the IBM SP2 parallel computer using the PVM message passing library as an example.