Kim Strohbehn

Current-mode subthreshold MOS circuits for analog VLSI neural systems

An overview of the current-mode approach for designing analog VLSI neural systems in subthreshold CMOS technology is presented. Emphasis is given to design techniques at the device level using the current-controlled current conveyor and the translinear principle. Circuits for associative memory and silicon retina systems are used as examples. The design methodology and how it relates to actual biological microcircuits are discussed.

CRISM (Compact Reconnaissance Imaging Spectrometer for Mars) on MRO (Mars Reconnaissance Orbiter)

CRISM (Compact Reconnaissance Imaging Spectrometer for Mars) is a hyperspectral imager that will be launched on the MRO (Mars Reconnaissance Orbiter) spacecraft in August 2005. MRO’s objectives are to recover climate science originally to have been conducted on the Mars Climate Orbiter (MCO), to identify and characterize sites of possible aqueous activity to which future landed missions may be sent, and to characterize the composition, geology, and stratigraphy of Martian surface deposits. MRO will operate from a sun-synchronous, near-circular (255x320 km altitude), near-polar orbit with a mean local solar time of 3 PM. CRISM’s spectral range spans the ultraviolet (UV) to the mid-wave infrared (MWIR), 383 nm to 3960 nm. The instrument utilizes a Ritchey-Chretien telescope with a 2.12° field-of-view (FOV) to focus light on the entrance slit of a dual spectrometer. Within the spectrometer, light is split by a dichroic into VNIR (visible-near-infrared, 383-1071 nm) and IR (infrared, 988-3960 nm) beams. Each beam is directed into a separate modified Offner spectrometer that focuses a spectrally dispersed image of the slit onto a two dimensional focal plane (FP). The IR FP is a 640 x 480 HgCdTe area array; the VNIR FP is a 640 x 480 silicon photodiode area array. The spectral image is contiguously sampled with a 6.6 nm spectral spacing and an instantaneous field of view of 61.5 μradians. The Optical Sensor Unit (OSU) can be gimbaled to take out along-track smear, allowing long integration times that afford high signal-to-noise ratio (SNR) at high spectral and spatial resolution. The scan motor and encoder are controlled by a separately housed Gimbal Motor Electronics (GME) unit. A Data Processing Unit (DPU) provides power, command and control, and data editing and compression. CRISM acquires three major types of observations of the Martian surface and atmosphere. In Multispectral Mapping Mode, with the gimbal pointed at planet nadir, data are collected at frame rates of 15 or 30 Hz. A commandable subset of wavelengths is saved by the DPU and binned 5:1 or 10:1 cross-track. The combination of frame rates and binning yields pixel footprints of 100 or 200 m. In this mode, nearly the entire planet can be mapped at wavelengths of key mineralogic absorption bands to select regions of interest. In Targeted Mode, the gimbal is scanned over ±60° from nadir to remove most along-track motion, and a region of interest is mapped at full spatial and spectral resolution. Ten additional abbreviated, pixel-binned observations are taken before and after the main hyperspectral image at longer atmospheric path lengths, providing an emission phase function (EPF) of the site for atmospheric study and correction of surface spectra for atmospheric effects. In Atmospheric Mode, the central observation is eliminated and only the EPF is acquired. Global grids of the resulting lower data volume observation are taken repeatedly throughout the Martian year to measure seasonal variations in atmospheric properties.

Analog VLSI neuromorphic image acquisition and pre-processing systems

Abstract We consider the problem of automatic object recognition by small, light-weight, low power, hardware systems. We abstract from biological function and organization and propose hardware architectures and a design methodology to engineer such hardware. Robust, miniature, and energetically efficient VLSI systems for AOR can ultimately be achieved by following a path which optimizes the design at and between all levels of system integration, i.e., from devices and circuit techniques all the way to algorithms and architectural level considerations. By way of example, we discuss two experimental systems for image acquisition and preprocessing fabricated in standard CMOS processes. The first one is a large scale analog system, a contrast sensitive silicon retina, with over 590, 000 transistors operating in subthreshold CMOS. The second system is a mixed analog-digital system for image acquisition and tracking compensation that incorporates a contrast sensitive silicon retina in the image sensing area.

Silicon retina for motion computation

An analog VLSI processor for motion computation is presented. It is based on the Hassenstein-Reichardt-Poggio model for information processing in the visual system of the fly. The authors show how neural network models can be mapped on silicon integrated circuits for performing tasks that can not be handled efficiently by digital computing machinery. The design is based on current-mode subthreshold MOS circuits using device-level design and exploiting the translinear property of the MOS transistor. Experimental results from fabricated chips are presented.<<ETX>>

Analog VLSI implementation of the Hassenstein-Reichardt-Poggio models for vision computation

The engineering of analog VLSI processors for computer vision is discussed. These are based on the Hassenstein-Reichardt-Poggio models for information processing in the visual systems of the fly. It is shown how neural network models can be mapped on silicon integrated circuits for performing tasks that can be handled efficiently by digital computing machinery. Hardware architectures for both position and motion computation are described.<<ETX>>

A silicon retina for 2-D position and motion computation

A chip which simultaneously computes image centroid and displacement from a fixed reference point was fabricated and was fully functional. Photoreceptors, image preprocessing, centroid, and displacement computations were integrated on a single die along with circuitry to generate NTSC standard video.

Winner-takes-all associative memory: a Hamming distance vector quantizer

We present a design methodology for mapping neuralyinspired algorithms for vector quantization, into VLSI hardware.We describe the building blocks used: memory cells, current conveyors,and translinear circuits. We use the basic building blocks todesign an associative processor for bit-pattern classification;a high-density memory based neuromorphic processor. Operatingin parallel, the single chip system determines the closest match,based on the Hamming distance, between an input bit pattern andmultiple stored bit templates; ties are broken arbitrarily. Energyefficient processing is achieved through a precision-on-demandarchitecture. Scalable storage and processing is achieved througha compact six transistor static RAM cell/ALU circuit. The singlechip system is programmable for template sets of up to 124 bitsper template and can store up to 116 templates (total storagecapacity of 14 Kbits). An additional 604 bits of auxiliary storageis used for pipelining and fault tolerance re-configuration capability.A fully functional 6.8 mm by 6.9 mmchip has been fabricated in a standard single–poly, double–metal2.0µmn–well CMOS process.

SPICE macro models for annular MOSFETs

MOSFETs with annular, or enclosed, geometries are now finding frequent use in rad-hard by design (RHBD) approaches to designing custom CMOS ASICs for aerospace applications. Unfortunately, these devices are not accurately modeled by the BSIM3 models normally provided for devices with ordinary rectangular gates. We present a SPICE macro model for an annular n-channel MOSFET to account for the annular geometry effects on gate overlap capacitance and output conductance.

An associative memory integrated system for character recognition

An associative memory chip is used for fast, robust character recognition. Operating in parallel, the chip determines the closest match between an input bit pattern and multiple stored bit patterns based on the Hamming distance; ties are broken arbitrarily. The chip is programmable for bit-mapped fonts of up to 124 bits per character and can store up to 116 characters. A fully functional 6.8 mm by 6.9 mm chip has been fabricated in a standard single-poly, double-metal 2.0 /spl mu/m n-well CMOS process.<<ETX>>

A sampled-data motion chip

An analog CMOS VLSI prototype for a visual motion detector was fabricated and tested. This 1-D implementation computes image displacement from a fixed reference point and is suitable for eventual inclusion in an image stabilization system. The chip uses a correlation-based algorithm similar to that proposed by Reichardt (1961).<<ETX>>